Changeset 247 for anr/section-3.1.tex

Timestamp:

Feb 17, 2010, 2:27:40 PM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-3.1.tex (modified) (1 diff)

anr/section-3.1.tex

@@ -79 +79 @@
 In addition, \xilinx System Generator and SOPC Builder are closed world
 since each one imposes their own IPs which are not interchangeable.
+%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
+%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
+%processor,  bus core, ...) as well as incorporate their own IP.
+%Designers can then generate a synthesized netlist, simulation test bench and custom
+%software library that reflect the hardware configuration.
+%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
+%simulate the platform at a high design level (systemC). 
+%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
+%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
+%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
+%coprocessors from a C++ description.
+%Nevertheless, they can only deal with data dominated applications and they do not handle
+%the platform level.
+%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
+%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
+%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
+%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
+%\xilinx pre-optimized macro-cells.
+%However, this tool targets only DSP based algorithms.
+%\\
+%Consequently, a designer developping an embedded system needs to master four different
+%design environments:
+%\begin{enumerate}
+%  \item a virtual prototyping environment such as SoCLib for system level exploration,
+%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
+%  from \xilinx) to define the hardware architecture,
+%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
+%        coprocessor synthesis,
+%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
+%\end{enumerate}
+%Furthermore, mixing these tools requires an important interfacing effort and this makes
+%the design process very complex and achievable only by designers skilled in many domains.
 
 \subsubsection{High Level Synthesis}