Changeset 237 for anr/section-3.1.tex

Timestamp:

Feb 16, 2010, 5:24:12 PM (14 years ago)

Author:

coach

Message:

Paul coquilles

File:

• anr/section-3.1.tex (modified) (5 diffs)

anr/section-3.1.tex

@@ -8 +8 @@
 \subsubsection{High Performance Computing}
 % Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language
-High-Performance Computing (HPC) world is composed of three main families of architectures:
+The High-Performance Computing (HPC) world is composed of three main families of architectures:
 many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
-The two first families are dominating the market by taking benefit 
+The first  two families are dominating the market by taking benefit 
 of the strength and influence of mass-market leaders (Intel, Nvidia).
 %such as Intel for many-core CPU and Nvidia for GPGPU.
@@ -51 +51 @@
 \subsubsection{System Synthesis}
 Today, several solutions for system design are proposed and commercialized.
-The existing commercial or free tools does not
+The existing commercial or free tools do not
 cover the whole system synthesis process in a full automatic way. Moreover,
 they are bound to a particular device family and to IPs library.
@@ -84 +84 @@
 set of constraints (area, power, frequency, ...) to a micro-architecture at
 Register Transfer Level (RTL).
-Several academic and commercial tools are today available. Most common
+Several academic and commercial tools are today available. The most common
 tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the
 academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and
-CYNTHETIZER~\cite{cynthetizer} in commercial world.  Despite their
+CYNTHETIZER~\cite{cynthetizer} in the commercial world.  Despite their
 maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}:
 \begin{itemize}
@@ -98 +98 @@
 designs are multi-constrained, 
 Moreover, low power consumption constraint is mandatory for embedded systems. 
-However, it is not yet well handled or not handle at all by the synthesis tools already available,
+However, it is not yet well handled or not handled at all by the synthesis tools already available,
 \item The parallelism is extracted from initial algorithmic specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
@@ -106 +106 @@
 pipelining, current HLS tools do not provide support for design space exploration neither
 through automatic loop transformations nor through memory mapping,
-\item Despite they have the same input language (C/C++), they are sensitive to the style in
-which the algorithm is written. Consequently, engineering work is required to swap from 
+\item Despite having the same input language (C/C++), they are sensitive to the style in
+which the algorithm dis written. Consequently, engineering work is required to swap from 
 a tool to another,
 \item They do not respect accurately the frequency constraint when they target an FPGA device.
 Their error is about 10 percent. This is annoying when the generated component is integrated
-in a SoC since it will slow down the hole system.
+in a SoC since it will slow down the whole system.
 \end{itemize}
 Regarding these limitations, it is necessary to create a new tool generation reducing the gap