Changeset 25


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Timestamp:
Jan 10, 2010, 11:24:50 PM (14 years ago)
Author:
coach
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anr
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  • anr/anr.tex

    r23 r25  
    200200\end{itemize}}
    201201
    202 \subsubsection{Task 0}
    203 %\input{task-0}
     202\subsubsection{Task 0: \textit{Project Managment}}
     203\input{task-0}
    204204
    205205\subsubsection{Task 1: \textit{\backbone}}
  • anr/section-1.tex

    r21 r25  
    11% les objectifs globaux,
    2 A digital system is an application integrated into one or several chips.
    3 These chips can be embedded in devices such as a personal digital assistant
    4 (PDA), ambiant computing component, wireless sensor network (WSN). They can
    5 also be used on a board connected to a PC to accelerate an application like
    6 in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP).
    7 Digital system design has  been investigated since eighties by using Applications
     2During these last decades, the design of complex digital systems is more and more reserved
     3high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs
     4due to increasing NRE (Non Recurring-Engineering) charges. The market of digital systems is about
     54,600 M\$ today and is estimated to 5,600 M\$ in 2012.
     6Digital system design has been investigated since eighties by using Applications
    87Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
    9 multiprocessor machines or networks.  More recently, since the end of nineties,
    10 other technologies appeared like Very Large Instruction Word (VLIW), Application
    11 Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors
    12 SoC (MPSoC).
    13 \\
    14 During these last decades, digital systems are more and more reserved
    15 to major companies targeting high volume market due to the design and fabrication
    16 costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges.
    17 Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
     8multiprocessor machines or networks.  Other technologies appeared like Very Large
     9Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP).
     10Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies
     11and thus requieres to design System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
     12Nowadays, Field Programmable Gate Arrays (FPGA), such like Virtex5 from Xilinx
    1813and Stratix4 from Altera, can implement a complete SoC with multiple processors and
    1914several coprocessors for less than 10K euros per device.
    2015In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
    21 Co-design, High-Level Synthesis...) become mature and allow to
    22 automate design and to drastically decrease its cost in terms of man power.
     16Co-design, High-Level Synthesis...) become mature and allow to automate the design of digital
     17systems and to drastically decrease their cost in terms of man power.
    2318Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
    24 enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices,
    25 to prototype complete complex embedded systems, to realize HPC or HSSP applications.
     19enterprises (SMEs) and major companies to get into new, low and medium volume markets,
     20to design highly innovative devices and to prototype complete digital systems.
    2621\par
    27 The objective of COACH is to provide an environment to design emmbedded systems and
    28 HPC applications on FPGA devices. The COACH framework will allow designer to explore various
    29 software/hardware partitioning scenario of the target application through timing and functional
    30 simulations and to generate automatically both the software and the
    31 synthesizable description of the hardware. Exploration and design are mainly
    32 driven by throughput, latency and/or power consumption criteria.
     22The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
     23complex digital systems on FPGA devices.  A digital system is an application integrated into one or
     24several chips. These chips can be embedded in devices such as a personal digital assistant (PDA),
     25ambiant computing component, wireless sensor network (WSN). They can also be used on a board connected
     26to a PC to accelerate an application like in High-Performance Computing (HPC) and in High-Speed Signal
     27Processing (HSSP).
     28
     29COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
     30K\euro) and reduces drastically them. So one can expect that tools targeting FPGA and dedicated to software developpers
     31will gain market share over Multi-core CPUs and GPUs HPC based solutions.
     32Moreover this market can also be boosted by small and even very small new companies
     33that will be able to propose embedded system and accelerating solutions for standard
     34software applications with acceptable prices.\\
     35
     36The main idea is to increase the design productivity by selecting a given flexible architectural template
     37and targeting the area of complex digital systems. This project involves the development of methodologies and
     38tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC)
     39of whole systems, by taking into account different application constraints (power consumption, throughput, latency...).
     40The project will also optimize an
     41important interface, usually not taken into account, between the high-level synthesis and the implementation
     42techniques on physical targets and the associated low level tools (logic synthesis and compilation).
     43The flow will allow, from a high-level specification (written in C language), to estimate, analyze, optimize the
     44performances and finally implement a real architecture. The COACH framework will allow the designer to explore various
     45software/hardware partitioning scenario of the target application through timing and functional simulations and to
     46generate automatically both the software and the synthesizable description of the hardware.
     47
     48%verrous scientifiques et techniques
    3349The main contributions of the project are:
    3450\begin{itemize}
     
    5672source-level transformations (loop transformations and memory optimisation) will be provided.
    5773This will allow to further explore the micro-architectural design space.
     74HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs.
     75data dominated). The HLS tools of COACH will support a common language and coding style to avoid engineering
     76work to the designer.
     77\item Communication interface: Coach will define and implement HW/SW communication management and define APIs
     78enabling communication between processors, processor/coprocessors,  FPGA and PC.
    5879\end{itemize}
    5980%In HPC, the kind of targeted application is an existing one running on PC.
     
    6182%SoC implemented on a FPGA plugged to the PC bus.\\
    6283%FIXME licence a speficier
    63 The COACH environment will be designed to abstract the hardware as much as possible to the end user.
     84
     85COACH will be designed to abstract the hardware as much as possible to the end user.
    6486It will thus be mainly dedicated to system designers.
    65 Finally COACH will be developped under the General Public Licence for the software tools.
    66 and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture.
    67 %The COACH architectural templates will be freely distributed.
    68 %
    69 % verrous scientifiques et techniques
    70 \mbox{}\vspace*{.9ex}\par
    71 System design is a very complex task this project will simplify as much as possible.
    72 For this purpose the following scientific and technological barriers will be addressed:
    73 \begin{itemize}
    74 \item The clock frequency of the coprocessors generated by the HLS must respect
    75 the frequency of the processors and the system bus.
    76 \item HLS tools are sensitive to the coding style of the input specification
    77 and the domain they target (control vs. data dominated). The HLS tools of COACH must have a
    78 common language and coding style to avoid engineering work to the designer.
    79 \item The main problem in HPC comes from timing performance and implementation of the communication
    80 between the PC and the FPGA.
    81 %FIXME: a completer loop tranfrom?, ASIP?, ...
    82 \end{itemize}
    83 %
     87
     88
     89
    8490% le programme de travail
    8591\vspace*{.9ex}\par
    86 COACH is the result of the will of several laboratories to unify their know
    87 hows and skills in the following domains: Operating system and hardware
     92
     93The COACH project targets fundamental issues related to design methodologies for
     94digital systems by providing estimation, exploration and design tools targeting both
     95performance and power optimization at all the abstraction levels of the flow (system,
     96architecture, algorithm and logic).
     97
     98To reach this ambitious aim, this project will lean on the experience and the complementariness
     99of partners in the following domains: Operating system and hardware
    88100communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
    89101HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
     
    92104SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
    93105ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
     106
    94107The project objective is to enhance and seamlessly integrate these tools into
    95108a unique open source framework.
    96 %masking these domains and its different tools to the system designer.
    97109The main steps of this project are:
    981101) Definition of the user inputs: application description as set of communicating tasks, each
     
    106118%FIXME : a completer
    107119\par
     120
     121The two major FPGA companies Altera and Xilinx expect this by supporting
     122and participating in this project.
    108123The role of the industrial partners BULL, THALES, XXX is to provide real
    109124benchmarks to guide the design of the framework and to prove that COACH is
    110125usuable and cover a large spectrum of applications.
    111 %
    112 % les retombées scientifiques, techniques et économiques
    113 \vspace*{.9ex}\par
    114 The main scientific contributions of the project are:
    115 to make high-level synthesis an elementary tool of system design,
    116 to unify various synthesis techniques (same input and output formats)
    117 allowing the designer to swap from one to an other and even to chain them
    118 without rewritting effort,
    119 to provide a system description independent of the target architecture and
    120 the FPGA family.
    121 \par
    122 The market of embedded system and HPC is about 4,600 M\$ today and is
    123 estimated to 5,600 M\$ in 2012.
    124 This market is dominated by Multi-core CPUs based solution and is controlled
    125 by major companies that can support the very high Non Recurring Engineering (NRE)
    126 costs involved in designing such system.
    127 Small and medium companies can only be present in this market with GPUs based solutions that have
    128 low NRE costs but limit the application domains.\\
    129 COACH reduces the NRE costs to the design costs (the FPGA device being only a few
    130 K\euro) and reduces drastically them.
    131 So one can expect that tools targeting FPGA and dedicated to software developpers
    132 will gain market share over Multi-core CPUs and GPUs HPC based solutions.
    133 Moreover this market can also be boosted by small and even very small new companies
    134 that will be able to propose embedded system and accelerating solutions for standard
    135 software applications with acceptable prices.\\
    136 The two major FPGA companies Altera and Xilinx expect this by supporting
    137 and participating in this project.
    138126
     127The COACH arhitectural templates will be freely distributed for non commercial use.
     128COACH will be developped under the General Public Licence for the software tools.
     129
  • anr/section-2.2.tex

    r19 r25  
    1 The aim of this project is to propose an open-source framework for
    2 architecture synthesis targeting mainly field programmable gate array
    3 circuits (FPGA).
    4 \\ % LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
    5 To evaluate the different architectures, the project uses the prototyping
    6 platform of the SoCLIB ANR project (2006-2009).
     1
     2% Relevance of the proposal
     3
     4The COACH proposal addresses directly the Embedded Systems of
     5the ARPEGE program, aiming at providing solutions to the societal/economical challenges by
     6providing the industry the novel design capabilities enabling them to increase their
     7design productivity with design exploration and synthesis methods that are placed on top
     8of the stat-of-theart methods, and thus, allowing the industry to better cope with the
     9complexity of designed digital systems.
     10\par
     11COACH will also contribute to the following strategic objectives of the ARPEGE program:
     12COACH will specifically contribute to enable the building of open development and run-time
     13environments for software and services, interoperable middleware and tools to support
     14developers in the production of embedded software, through all phases of the software lifecycle,
     15from requirements analysis until deployment and maintenance.
     16\\
     17More specifically, COACH focuses on:
     18\begin{itemize}
     19\item High level methods and concepts (esp. requirements and architectural level) for system
     20design, development and integration, addressing complexity aspects and modularity.
     21\item Open and modular development environments, enabling flexibility and extensibility by
     22means of new or sector-specific tools and ensuring consistency and traceability along the
     23development lifecycle.
     24\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
     25environment, suitable for co-operative and distributed development.
     26\end{itemize}
     27COACH outcome will contribute to strengthen Europe's competitive position by developing
     28technologies and methodologies for product development, focusing (in compliance with the
     29scope of the above program) on technologies, engineering methodologies, novel tools,
     30methods which facilitate resource use efficiency. The approaches and tools to be developed
     31in COACH will enable new and emerging information technologies for the development,
     32manufacturing and integration of devices and related software into end-products.
     33\\
     34This project proposes an open-source framework for architecture synthesis targeting
     35Field Programmable Gate Array circuits (FPGA).
     36\par
     37% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
     38To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
    739\\ % LIEN AVEC AUTRES PROJETS: IRISA
    840The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing
    9 joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern 
     41joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
    1042extraction algorithms and datapath merging techniques to the synthesis of customized
    1143ASIP processors.
    12 \\
     44\par
    1345On the HPC application side, we also hope to benefit from the experience in
    1446hardware acceleration of bioinformatic algorithms/workfows gathered by the
  • anr/section-2.tex

    r17 r25  
    1 An embedded system is an application integrated into one or several chips
    2 in order to accelerate it or to embedd it into a small device such as a personal
    3 digital assistant (PDA).
    4 This topic is investigated since 80s using Applications Specific Integrated
    5 Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
    6 multiprocessor machines or networks.
    7 More recently, since end of 90s, other technologies appeared like Very
    8 Large Instruction Word (VLIW), Application Specific Instruction Processors
    9 (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
     1The emerging complex and integrated heterogeneous embedded system platforms require
     2adequate design methods able to efficiently model, explore, analyze and design the ever complex SW
     3and HW architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing
     4performance requirements linked with a pressure to lower development cost and shorten time-tomarket,
     5will have to adopt new design methods and flows able to keep pace with the increasing
     6complexity of design problems. Such methods, addressing these challenges starting from high levels of
     7abstraction, will have to perform large solution space exploration jointly for SW and HW (possibly
     8reconfigurable), involving almost marginal design effort and offering a high predictability of results
     9with respect to cost- and performance-functions.
     10Current design methodologies provide quite low-level abstraction capabilities. However in a few years
     11from now tens of programmable processors will be embedded in an IC with together over 100M
     12transistors adding to the complexity of the problem of architecting such systems. Taking into account
     13that the complexity of the SW part is pacing up at an even faster speed, current solutions to perform
     14design space exploration, mainly manually based, by no means do supply a performance of adequate
     15sufficiency.
     16Consequently, there is an urgent need to leverage system level
     17exploration through the use of a high level specification of the application and an early design
     18space exploration steps. The first system oriented approaches are appearing, among which those
     19based on C/C++ and SystemC are most popular. Such approaches can take place before and/or after
     20the co-design or architecture refinement steps and targets the design space pruning in order to fully
     21exploit potential solutions that meet design and application constraints (power, latency,
     22throughput) within the design and market timeframe.
    1023\\
    11 During these last decades embedded system was reserved to major industrial
    12 companies targeting high volume market due to the design and fabrication
    13 costs.
    14 Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
    15 and Stratix4 from Altera, can implement a SoC with multiple processors and
    16 several coprocessors for less than 10K euros per item. In addition, High
    17 Level Synthesis (HLS) becomes more mature and allows to automate design and
    18 to drastically decrease its cost in terms of man power. Thus, both FPGA and
    19 HLS tend to spread over HPC for small companies targeting low volume
    20 markets.
     24Thus, new system-level design flows need to be developed, enabling the exploration of an application
     25independently of the implementation, this almost at the beginning of the design process. A
     26fundamental element of this evolution is the definition of abstraction layers that should allow the
     27systematic re-use of SW and HW components at the system level driven by performance estimation
     28and analysis. It is the context in which the COACH modeling and estimation methods combined with
     29compilers and design space exploration techniques. This approach will cause a real breakthrough in
     30the embedded system design methodology, i.e. one of the radical innovations.
     31\\
     32The reason is that COACH precedes the use of high-level design tools in the embedded
     33systems design flows. In that way, it will make possible a real and efficiently combined
     34exploitation of high-level synthesis tools, parallelising approaches and compilers, already
     35available on the market. These tools and approaches are not yet massively adopted, precisely
     36because this decisive design step is missing. COACH will indeed permit (i) to predict and
     37control implementation optimizations, (ii) to target multiple implementation technologies
     38(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
     39and low-level design tools in a unique seamless design flow.
     40\\
     41The performance estimation methods combined with the design space exploration techniques will
     42finally allow the design process to start from system level specification and automatically explore the
     43potential architectures in order to find out the optimal implementation in a shorter design time and at
     44a lower global cost.
    2145\par
    2246To get an efficient embedded system, designer has to take into account
  • anr/section-4.2.tex

    r12 r25  
    1 % FIXME EN FRANCAIS ET PAS A JOUR
    2 \mustbecompleted{
    3 Différents outils seront mis en place pour assurer le succès du projet, et
    4 faciliter la coopération entre les partenaires.
    5 \\
    6 La coordination générale du projet sera assurée par l'UBS/Lab-STICC. Le
    7 coordinateur assurera le management général du projet, il veillera au
    8 respect du plan d'exécution des travaux, et à la remise en temps voulu des
    9 fournitures. Il sera l'interlocuteur privilégié pour l'ANR, et représentera
    10 les autres partenaires du projet.
    11 \\
    12 La coordination technique sera assurée par l'UBS/Lab-STICC, qui sera chargé
    13 de garantir la cohérence scientifique et technique du projet au travers
    14 d'organisation des de Réunions Techniques d'Avancement, du suivi et de la
    15 centralisation des fournitures, etc.
    16 \\
    17 Des Réunions Techniques d'Avancement, regroupant tous les partenaires
    18 seront organisées une fois par trimestre. Ces réunions ont pour but de
    19 favoriser la circulation des informations techniques entre les différents
    20 partenaires. Des réunions de travail supplémentaires seront planifiées
    21 par chaque responsable de sous projet.
    22 \\
    23 Les outils logiciels développés par les partenaires académiques dans le
    24 cadre du projet XXXXX seront distribués en tant que logiciel libre. Ceci
    25 facilitera la circulation des informations techniques au sein mais aussi en
    26 dehors du projet.
    27 \\
    28 Pour faciliter la circulation des informations techniques et la coopération
    29 entre les différents partenaires, un serveur WEB accessible par Intranet
    30 sera mis en place par l'UBS/Lab-STICC dès le démarrage du projet. Ce
    31 serveur permettra à tous les partenaires d'accéder à la documentation
    32 technique partagée, ainsi qu'aux présentations effectuées à l'occasion des
    33 réunions techniques trimestrielles, etc.
    34 \\
    35 La validation des fournitures de ce projet sera assurée de façon continue
    36 par les auteurs de celles-ci ainsi que par les partenaires qui auront en
    37 charge soit l'intégration de ces fournitures soit produiront eux-même des
    38 éléments en relation avec la fourniture à valider.
    39 \\
    40 Le suivi du projet sera fait de la façon suivante:
    41 \\
    42 Un compte-rendu d'activité sera communiqué tous les 6 mois au chargé du
    43 dossier par le coordinateur du projet. Ce rapport comprendra une
    44 contribution par partenaire et un document rédigé par le coordinateur.
    45 \\
    46 Un rapport sur chaque jalon sera fourni à T0+12, T0+24. Ce rapport donnera
    47 l'état d'avancement du projet avec de indicateurs tels que:
    48 1.respect des livraisons techniques (modèles et outils) \\
    49 2.conformité des livraisons aux spécifications \\
    50 3.dates de livraison des fournitures  \\
    51 4.état d'avancement du projet \\
    52 5.risques et actions correctives \\
    53 \\
    54 Un rapport final sera rendu au terme du projet a T0 + 36
    55 \\
    56 Une revue de projet annuelle, avec l'administration, sera organisée afin de
    57 faire un bilan détaillé de l'avancement du projet. Il pourra être décidé en
    58 commun des évolutions éventuelles du projet.
    59 }
     1\begin{description}
     2\item[Project management structure]
     3First of all, a good management requires that each task is assigned to a Task Leader.
     4The Task Leaders assist the project leader in the technical organization, effort
     5management, of the co-operation and the reporting of the progress. Each month the Task
     6Leaders have to send to the project leader short update report with the
     7main high-lights, major opportunities and treats according to the work-plan.
     8Therefore, each Partner has the responsibility to monthly inform the task Leaders of the
     9current development of the \ST it has in charge.
     10COACH will be organized in 8 tasks whose interactions are presented in
     11Figure~\ref{dependence-task}.
     12
     13\item[Scientific and Technical Reports]
     14For every yearly and half period report, milestone or deliverable, a written progress
     15report has to be provided by the task leader to coordinator for integration in the
     16contractual reports.
     17
     18\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation]
     19The partners will have to respect to work under the NDA constraints.
     20Prior Intellectual Property remains property of the concerned partners.
     21The exploitation of the results obtained in the project and by each partner involved in the consortium will
     22follow the rules written the articles of the Consortium Agreement accepted and signed by
     23each partner at most 6 months after the project kick-off.
     24To manage the exploitation and dissemination plan within the project, six
     25monthly meetings will analyze the intentions from the consortium (patent, publication...).
     26
     27\item[Management Tools]
     28In order to permit a good management, before the kick-off meeting, the different partners
     29will have to identify namely (and with their address, phone, fax and e-mail):
     30\begin{itemize}
     31  \item The financial and administrative person authorized and the legal person authorized
     32or at least the scientific and technical.
     33  \item A complete and detailed list will be communicated to each partner and to public
     34  Authority.
     35  \item Mailing lists used by the partners for the day to day communication.
     36\end{itemize}
     37Following the requests and the information received by the partner's representatives and
     38their financial and legal department, a Consortium Agreement will be realized and will
     39deal mainly with all aspects of the relationships between partners, including legal
     40aspects, property rights and further exploitation of the results.
     41Moreover, the management rules of the project will also be defined clearly in this major
     42document (decision level, reporting systems, red flag cases).  A first draft of this
     43document will be introduced to each partner during the kick-off meeting.
     44
     45\item[Project follow-ups]
     46The basic communication between single project partners will be carried out by means of an Information System (web site), which will be developed and introduced at the very beginning of the project implementation.
     47All scientific and administrative data related to the project will be collected and
     48treated within a specific e-management plate-form accessible directly by the project web
     49site by an individual login and pass-word.
     50The web site will have a few levels of accessibility starting with completely free access,
     51open to broad public up to internal materials available only for members of the consortium
     52for the e-management area.
     53This communication tools will permit to perform all the reports and to follow as well as
     54possible all the tasks.
     55
     56\item[Project monitoring]
     57For this project format and size, a 12 months review by ANR, based on a yearly progress
     58report incorporating milestones reports and deliverables, seems optimum.
     59The internal consortium meetings will be six monthly, including a kick-off meeting at the
     60start of the project, in our eyes the most important of all, as it phases the partners for
     61the start of the project on.
     62\end{description}
  • anr/task-1.tex

    r21 r25  
    1 %\def\TBresp{\coussy}
    2 %\def\TBresplab{\labsticc}
    3 %\def\TBpartner{\alllabs,\allcompagnies}
    4 
    51\begin{taskinfo}
    62\let\UPMC\leader
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