Changeset 25

Timestamp:

Jan 10, 2010, 11:24:50 PM (15 years ago)

Author:

coach

Message:

 

Location:

anr

Files:

• anr.tex (modified) (1 diff)
• section-1.tex (modified) (5 diffs)
• section-2.2.tex (modified) (1 diff)
• section-2.tex (modified) (1 diff)
• section-4.2.tex (modified) (1 diff)
• task-0.tex (added)
• task-1.tex (modified) (1 diff)

anr/anr.tex

@@ -200 +200 @@
 \end{itemize}}
 
-\subsubsection{Task 0}
-%\input{task-0}
+\subsubsection{Task 0: \textit{Project Managment}}
+\input{task-0}
 
 \subsubsection{Task 1: \textit{\backbone}}

anr/section-1.tex

@@ -1 +1 @@
 % les objectifs globaux, 
-A digital system is an application integrated into one or several chips.
-These chips can be embedded in devices such as a personal digital assistant 
-(PDA), ambiant computing component, wireless sensor network (WSN). They can 
-also be used on a board connected to a PC to accelerate an application like 
-in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP). 
-Digital system design has  been investigated since eighties by using Applications 
+During these last decades, the design of complex digital systems is more and more reserved 
+high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs 
+due to increasing NRE (Non Recurring-Engineering) charges. The market of digital systems is about 
+4,600 M\$ today and is estimated to 5,600 M\$ in 2012.
+Digital system design has been investigated since eighties by using Applications 
 Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on 
-multiprocessor machines or networks.  More recently, since the end of nineties, 
-other technologies appeared like Very Large Instruction Word (VLIW), Application 
-Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors 
-SoC (MPSoC).
-\\
-During these last decades, digital systems are more and more reserved 
-to major companies targeting high volume market due to the design and fabrication
-costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges.
-Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
+multiprocessor machines or networks.  Other technologies appeared like Very Large 
+Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP). 
+Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies 
+and thus requieres to design System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
+Nowadays, Field Programmable Gate Arrays (FPGA), such like Virtex5 from Xilinx
 and Stratix4 from Altera, can implement a complete SoC with multiple processors and
 several coprocessors for less than 10K euros per device.
 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 
-Co-design, High-Level Synthesis...) become mature and allow to
-automate design and to drastically decrease its cost in terms of man power.
+Co-design, High-Level Synthesis...) become mature and allow to automate the design of digital 
+systems and to drastically decrease their cost in terms of man power.
 Thus, coupling both FPGA and ESL methodologies will soon allow small and medium 
-enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices, 
-to prototype complete complex embedded systems, to realize HPC or HSSP applications.
+enterprises (SMEs) and major companies to get into new, low and medium volume markets, 
+to design highly innovative devices and to prototype complete digital systems.
 \par
-The objective of COACH is to provide an environment to design emmbedded systems and
-HPC applications on FPGA devices. The COACH framework will allow designer to explore various 
-software/hardware partitioning scenario of the target application through timing and functional
-simulations and to generate automatically both the software and the
-synthesizable description of the hardware. Exploration and design are mainly 
-driven by throughput, latency and/or power consumption criteria.
+The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
+complex digital systems on FPGA devices.  A digital system is an application integrated into one or 
+several chips. These chips can be embedded in devices such as a personal digital assistant (PDA), 
+ambiant computing component, wireless sensor network (WSN). They can also be used on a board connected 
+to a PC to accelerate an application like in High-Performance Computing (HPC) and in High-Speed Signal 
+Processing (HSSP).
+
+COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
+K\euro) and reduces drastically them. So one can expect that tools targeting FPGA and dedicated to software developpers
+will gain market share over Multi-core CPUs and GPUs HPC based solutions.
+Moreover this market can also be boosted by small and even very small new companies
+that will be able to propose embedded system and accelerating solutions for standard
+software applications with acceptable prices.\\
+
+The main idea is to increase the design productivity by selecting a given flexible architectural template 
+and targeting the area of complex digital systems. This project involves the development of methodologies and 
+tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC) 
+of whole systems, by taking into account different application constraints (power consumption, throughput, latency...). 
+The project will also optimize an 
+important interface, usually not taken into account, between the high-level synthesis and the implementation 
+techniques on physical targets and the associated low level tools (logic synthesis and compilation). 
+The flow will allow, from a high-level specification (written in C language), to estimate, analyze, optimize the 
+performances and finally implement a real architecture. The COACH framework will allow the designer to explore various 
+software/hardware partitioning scenario of the target application through timing and functional simulations and to 
+generate automatically both the software and the synthesizable description of the hardware. 
+
+%verrous scientifiques et techniques
 The main contributions of the project are:
 \begin{itemize} 
@@ -56 +72 @@
 source-level transformations (loop transformations and memory optimisation) will be provided. 
 This will allow to further explore the micro-architectural design space.
+HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs. 
+data dominated). The HLS tools of COACH will support a common language and coding style to avoid engineering 
+work to the designer.
+\item Communication interface: Coach will define and implement HW/SW communication management and define APIs
+enabling communication between processors, processor/coprocessors,  FPGA and PC.
 \end{itemize}
 %In HPC, the kind of targeted application is an existing one running on PC.
@@ -61 +82 @@
 %SoC implemented on a FPGA plugged to the PC bus.\\
 %FIXME licence a speficier
-The COACH environment will be designed to abstract the hardware as much as possible to the end user.
+
+COACH will be designed to abstract the hardware as much as possible to the end user.
 It will thus be mainly dedicated to system designers.
-Finally COACH will be developped under the General Public Licence for the software tools.
-and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture.
-%The COACH architectural templates will be freely distributed.
-%
-% verrous scientifiques et techniques
-\mbox{}\vspace*{.9ex}\par
-System design is a very complex task this project will simplify as much as possible. 
-For this purpose the following scientific and technological barriers will be addressed:
-\begin{itemize}
-\item The clock frequency of the coprocessors generated by the HLS must respect
-the frequency of the processors and the system bus.
-\item HLS tools are sensitive to the coding style of the input specification 
-and the domain they target (control vs. data dominated). The HLS tools of COACH must have a 
-common language and coding style to avoid engineering work to the designer.
-\item The main problem in HPC comes from timing performance and implementation of the communication 
-between the PC and the FPGA.
-%FIXME: a completer loop tranfrom?, ASIP?, ...
-\end{itemize}
-%
+
+
+
 % le programme de travail
 \vspace*{.9ex}\par
-COACH is the result of the will of several laboratories to unify their know
-hows and skills in the following domains: Operating system and hardware
+
+The COACH project targets fundamental issues related to design methodologies for 
+digital systems by providing estimation, exploration and design tools targeting both 
+performance and power optimization at all the abstraction levels of the flow (system, 
+architecture, algorithm and logic).
+
+To reach this ambitious aim, this project will lean on the experience and the complementariness 
+of partners in the following domains: Operating system and hardware
 communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
 HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
@@ -92 +104 @@
 SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on 
 ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
+
 The project objective is to enhance and seamlessly integrate these tools into
 a unique open source framework. 
-%masking these domains and its different tools to the system designer. 
 The main steps of this project are:
 1) Definition of the user inputs: application description as set of communicating tasks, each
@@ -106 +118 @@
 %FIXME : a completer
 \par
+
+The two major FPGA companies Altera and Xilinx expect this by supporting
+and participating in this project.
 The role of the industrial partners BULL, THALES, XXX is to provide real
 benchmarks to guide the design of the framework and to prove that COACH is
 usuable and cover a large spectrum of applications.
-%
-% les retombées scientifiques, techniques et économiques
-\vspace*{.9ex}\par
-The main scientific contributions of the project are:
-to make high-level synthesis an elementary tool of system design,
-to unify various synthesis techniques (same input and output formats)
-allowing the designer to swap from one to an other and even to chain them
-without rewritting effort,
-to provide a system description independent of the target architecture and 
-the FPGA family.
-\par
-The market of embedded system and HPC is about 4,600 M\$ today and is
-estimated to 5,600 M\$ in 2012.
-This market is dominated by Multi-core CPUs based solution and is controlled
-by major companies that can support the very high Non Recurring Engineering (NRE)
-costs involved in designing such system.
-Small and medium companies can only be present in this market with GPUs based solutions that have
-low NRE costs but limit the application domains.\\
-COACH reduces the NRE costs to the design costs (the FPGA device being only a few
-K\euro) and reduces drastically them.
-So one can expect that tools targeting FPGA and dedicated to software developpers
-will gain market share over Multi-core CPUs and GPUs HPC based solutions.
-Moreover this market can also be boosted by small and even very small new companies
-that will be able to propose embedded system and accelerating solutions for standard
-software applications with acceptable prices.\\
-The two major FPGA companies Altera and Xilinx expect this by supporting
-and participating in this project.
 
+The COACH arhitectural templates will be freely distributed for non commercial use.
+COACH will be developped under the General Public Licence for the software tools.
+

anr/section-2.2.tex

@@ -1 @@
-The aim of this project is to propose an open-source framework for
-architecture synthesis targeting mainly field programmable gate array
-circuits (FPGA).
-\\ % LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
-To evaluate the different architectures, the project uses the prototyping
-platform of the SoCLIB ANR project (2006-2009).
+
+% Relevance of the proposal 
+
+The COACH proposal addresses directly the Embedded Systems of
+the ARPEGE program, aiming at providing solutions to the societal/economical challenges by
+providing the industry the novel design capabilities enabling them to increase their
+design productivity with design exploration and synthesis methods that are placed on top 
+of the stat-of-theart methods, and thus, allowing the industry to better cope with the 
+complexity of designed digital systems.
+\par
+COACH will also contribute to the following strategic objectives of the ARPEGE program:
+COACH will specifically contribute to enable the building of open development and run-time
+environments for software and services, interoperable middleware and tools to support
+developers in the production of embedded software, through all phases of the software lifecycle,
+from requirements analysis until deployment and maintenance.
+\\
+More specifically, COACH focuses on:
+\begin{itemize}
+\item High level methods and concepts (esp. requirements and architectural level) for system
+design, development and integration, addressing complexity aspects and modularity.
+\item Open and modular development environments, enabling flexibility and extensibility by
+means of new or sector-specific tools and ensuring consistency and traceability along the
+development lifecycle.
+\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
+environment, suitable for co-operative and distributed development.
+\end{itemize}
+COACH outcome will contribute to strengthen Europe's competitive position by developing
+technologies and methodologies for product development, focusing (in compliance with the
+scope of the above program) on technologies, engineering methodologies, novel tools,
+methods which facilitate resource use efficiency. The approaches and tools to be developed 
+in COACH will enable new and emerging information technologies for the development,
+manufacturing and integration of devices and related software into end-products.
+\\
+This project proposes an open-source framework for architecture synthesis targeting 
+Field Programmable Gate Array circuits (FPGA).
+\par
+% LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
+To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
 \\ % LIEN AVEC AUTRES PROJETS: IRISA
 The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing 
-joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern 
+joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
 extraction algorithms and datapath merging techniques to the synthesis of customized 
 ASIP processors.
-\\
+\par
 On the HPC application side, we also hope to benefit from the experience in
 hardware acceleration of bioinformatic algorithms/workfows gathered by the

anr/section-2.tex

@@ -1 @@
-An embedded system is an application integrated into one or several chips
-in order to accelerate it or to embedd it into a small device such as a personal 
-digital assistant (PDA).
-This topic is investigated since 80s using Applications Specific Integrated
-Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
-multiprocessor machines or networks.
-More recently, since end of 90s, other technologies appeared like Very
-Large Instruction Word (VLIW), Application Specific Instruction Processors
-(ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
+The emerging complex and integrated heterogeneous embedded system platforms require
+adequate design methods able to efficiently model, explore, analyze and design the ever complex SW
+and HW architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing
+performance requirements linked with a pressure to lower development cost and shorten time-tomarket,
+will have to adopt new design methods and flows able to keep pace with the increasing
+complexity of design problems. Such methods, addressing these challenges starting from high levels of
+abstraction, will have to perform large solution space exploration jointly for SW and HW (possibly
+reconfigurable), involving almost marginal design effort and offering a high predictability of results
+with respect to cost- and performance-functions.
+Current design methodologies provide quite low-level abstraction capabilities. However in a few years
+from now tens of programmable processors will be embedded in an IC with together over 100M
+transistors adding to the complexity of the problem of architecting such systems. Taking into account
+that the complexity of the SW part is pacing up at an even faster speed, current solutions to perform
+design space exploration, mainly manually based, by no means do supply a performance of adequate
+sufficiency.
+Consequently, there is an urgent need to leverage system level
+exploration through the use of a high level specification of the application and an early design
+space exploration steps. The first system oriented approaches are appearing, among which those
+based on C/C++ and SystemC are most popular. Such approaches can take place before and/or after
+the co-design or architecture refinement steps and targets the design space pruning in order to fully
+exploit potential solutions that meet design and application constraints (power, latency,
+throughput) within the design and market timeframe.
 \\
-During these last decades embedded system was reserved to major industrial
-companies targeting high volume market due to the design and fabrication
-costs.
-Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
-and Stratix4 from Altera, can implement a SoC with multiple processors and
-several coprocessors for less than 10K euros per item. In addition, High
-Level Synthesis (HLS) becomes more mature and allows to automate design and
-to drastically decrease its cost in terms of man power. Thus, both FPGA and
-HLS tend to spread over HPC for small companies targeting low volume
-markets.
+Thus, new system-level design flows need to be developed, enabling the exploration of an application
+independently of the implementation, this almost at the beginning of the design process. A
+fundamental element of this evolution is the definition of abstraction layers that should allow the
+systematic re-use of SW and HW components at the system level driven by performance estimation
+and analysis. It is the context in which the COACH modeling and estimation methods combined with 
+compilers and design space exploration techniques. This approach will cause a real breakthrough in 
+the embedded system design methodology, i.e. one of the radical innovations.
+\\
+The reason is that COACH precedes the use of high-level design tools in the embedded
+systems design flows. In that way, it will make possible a real and efficiently combined
+exploitation of high-level synthesis tools, parallelising approaches and compilers, already
+available on the market. These tools and approaches are not yet massively adopted, precisely
+because this decisive design step is missing. COACH will indeed permit (i) to predict and
+control implementation optimizations, (ii) to target multiple implementation technologies
+(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
+and low-level design tools in a unique seamless design flow.
+\\
+The performance estimation methods combined with the design space exploration techniques will
+finally allow the design process to start from system level specification and automatically explore the
+potential architectures in order to find out the optimal implementation in a shorter design time and at
+a lower global cost.
 \par
 To get an efficient embedded system, designer has to take into account

anr/section-4.2.tex

@@ -1 @@
-% FIXME EN FRANCAIS ET PAS A JOUR
-\mustbecompleted{
-Différents outils seront mis en place pour assurer le succès du projet, et
-faciliter la coopération entre les partenaires.
-\\
-La coordination générale du projet sera assurée par l'UBS/Lab-STICC. Le
-coordinateur assurera le management général du projet, il veillera au
-respect du plan d'exécution des travaux, et à la remise en temps voulu des
-fournitures. Il sera l'interlocuteur privilégié pour l'ANR, et représentera
-les autres partenaires du projet.
-\\
-La coordination technique sera assurée par l'UBS/Lab-STICC, qui sera chargé
-de garantir la cohérence scientifique et technique du projet au travers
-d'organisation des de Réunions Techniques d'Avancement, du suivi et de la
-centralisation des fournitures, etc.
-\\
-Des Réunions Techniques d'Avancement, regroupant tous les partenaires
-seront organisées une fois par trimestre. Ces réunions ont pour but de
-favoriser la circulation des informations techniques entre les différents
-partenaires. Des réunions de travail supplémentaires seront planifiées
-par chaque responsable de sous projet.
-\\
-Les outils logiciels développés par les partenaires académiques dans le
-cadre du projet XXXXX seront distribués en tant que logiciel libre. Ceci
-facilitera la circulation des informations techniques au sein mais aussi en
-dehors du projet.
-\\
-Pour faciliter la circulation des informations techniques et la coopération
-entre les différents partenaires, un serveur WEB accessible par Intranet
-sera mis en place par l'UBS/Lab-STICC dès le démarrage du projet. Ce
-serveur permettra à tous les partenaires d'accéder à la documentation
-technique partagée, ainsi qu'aux présentations effectuées à l'occasion des
-réunions techniques trimestrielles, etc.
-\\
-La validation des fournitures de ce projet sera assurée de façon continue
-par les auteurs de celles-ci ainsi que par les partenaires qui auront en
-charge soit l'intégration de ces fournitures soit produiront eux-même des
-éléments en relation avec la fourniture à valider.
-\\
-Le suivi du projet sera fait de la façon suivante: 
-\\
-Un compte-rendu d'activité sera communiqué tous les 6 mois au chargé du
-dossier par le coordinateur du projet. Ce rapport comprendra une
-contribution par partenaire et un document rédigé par le coordinateur.
-\\
-Un rapport sur chaque jalon sera fourni à T0+12, T0+24. Ce rapport donnera
-l'état d'avancement du projet avec de indicateurs tels que:
-1.respect des livraisons techniques (modèles et outils) \\
-2.conformité des livraisons aux spécifications \\
-3.dates de livraison des fournitures  \\
-4.état d'avancement du projet \\
-5.risques et actions correctives \\
-\\
-Un rapport final sera rendu au terme du projet a T0 + 36
-\\
-Une revue de projet annuelle, avec l'administration, sera organisée afin de
-faire un bilan détaillé de l'avancement du projet. Il pourra être décidé en
-commun des évolutions éventuelles du projet.
-}
+\begin{description}
+\item[Project management structure]
+First of all, a good management requires that each task is assigned to a Task Leader.
+The Task Leaders assist the project leader in the technical organization, effort
+management, of the co-operation and the reporting of the progress. Each month the Task
+Leaders have to send to the project leader short update report with the
+main high-lights, major opportunities and treats according to the work-plan.
+Therefore, each Partner has the responsibility to monthly inform the task Leaders of the
+current development of the \ST it has in charge.
+COACH will be organized in 8 tasks whose interactions are presented in
+Figure~\ref{dependence-task}.
+
+\item[Scientific and Technical Reports]
+For every yearly and half period report, milestone or deliverable, a written progress
+report has to be provided by the task leader to coordinator for integration in the
+contractual reports.
+
+\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation]
+The partners will have to respect to work under the NDA constraints.
+Prior Intellectual Property remains property of the concerned partners.
+The exploitation of the results obtained in the project and by each partner involved in the consortium will
+follow the rules written the articles of the Consortium Agreement accepted and signed by
+each partner at most 6 months after the project kick-off.
+To manage the exploitation and dissemination plan within the project, six
+monthly meetings will analyze the intentions from the consortium (patent, publication...).
+
+\item[Management Tools]
+In order to permit a good management, before the kick-off meeting, the different partners
+will have to identify namely (and with their address, phone, fax and e-mail):
+\begin{itemize}
+  \item The financial and administrative person authorized and the legal person authorized 
+or at least the scientific and technical.
+  \item A complete and detailed list will be communicated to each partner and to public
+  Authority.
+  \item Mailing lists used by the partners for the day to day communication.
+\end{itemize}
+Following the requests and the information received by the partner's representatives and
+their financial and legal department, a Consortium Agreement will be realized and will
+deal mainly with all aspects of the relationships between partners, including legal
+aspects, property rights and further exploitation of the results.
+Moreover, the management rules of the project will also be defined clearly in this major
+document (decision level, reporting systems, red flag cases).  A first draft of this
+document will be introduced to each partner during the kick-off meeting.
+
+\item[Project follow-ups]
+The basic communication between single project partners will be carried out by means of an Information System (web site), which will be developed and introduced at the very beginning of the project implementation.
+All scientific and administrative data related to the project will be collected and
+treated within a specific e-management plate-form accessible directly by the project web
+site by an individual login and pass-word.
+The web site will have a few levels of accessibility starting with completely free access,
+open to broad public up to internal materials available only for members of the consortium
+for the e-management area.
+This communication tools will permit to perform all the reports and to follow as well as
+possible all the tasks.
+
+\item[Project monitoring]
+For this project format and size, a 12 months review by ANR, based on a yearly progress
+report incorporating milestones reports and deliverables, seems optimum.
+The internal consortium meetings will be six monthly, including a kick-off meeting at the
+start of the project, in our eyes the most important of all, as it phases the partners for
+the start of the project on.
+\end{description}

anr/task-1.tex

@@ -1 @@
-%\def\TBresp{\coussy}
-%\def\TBresplab{\labsticc}
-%\def\TBpartner{\alllabs,\allcompagnies}
-
 \begin{taskinfo}
 \let\UPMC\leader