Changeset 27

Timestamp:

Jan 11, 2010, 7:51:00 AM (14 years ago)

Author:

coach

Message:

 

Location:

anr

Files:

• anr.sty (modified) (2 diffs)
• anr.tex (modified) (3 diffs)
• task-0.tex (modified) (2 diffs)
• task-1.tex (modified) (1 diff)
• task-2.tex (modified) (1 diff)
• task-3.tex (modified) (1 diff)
• task-4.tex (modified) (1 diff)
• task-5.tex (modified) (1 diff)
• task-6.tex (modified) (1 diff)

anr/anr.sty

@@ -16 +16 @@
 \let\UBS\disable%
 \let\UPMC\disable%
+\let\ALTERA\disable%
+\let\XILINX\disable%
 \let\BULL\disable%
 \let\THALES\disable%
@@ -27 +29 @@
   \ifx\TIMA\disable\let\TIMA\enable\fi%
   \ifx\UBS\disable\let\UBS\enable\fi%
+  \ifx\ALTERA\disable\let\ALTERA\enable\fi%
+  \ifx\XILINX\disable\let\XILINX\enable\fi%
   \ifx\BULL\disable\let\BULL\enable\fi%
   \ifx\THALES\disable\let\THALES\enable\fi%
   \ifx\ZIED\disable\let\ZIED\enable\fi%
 \fi%
-\def\@IRISA{\ifx\IRISA\disable{}\else\ifx\IRISA\enable{*}\else{l}\fi\fi}%
-\def\@CITI{\ifx\CITI\disable{}\else\ifx\CITI\enable{*}\else{l}\fi\fi}%
-\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{*}\else{l}\fi\fi}%
-\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{*}\else{l}\fi\fi}%
-\def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{*}\else{l}\fi\fi}%
-\def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{*}\else{l}\fi\fi}%
-\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{*}\else{l}\fi\fi}%
-\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{*}\else{l}\fi\fi}%
-\def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{*}\else{l}\fi\fi}%
-\begin{tabular}{|c|c|c|c|c|c|c|c|c|}\hline
-\irisa  & \citi  & \lip  & \tima  & \ubs  & \upmc  & \bull  & \thales  & \zied \\\hline
-\@IRISA & \@CITI & \@LIP & \@TIMA & \@UBS & \@UPMC & \@BULL & \@THALES & \@ZIED \\\hline
+\def\@leader{\begin{small}\textcolor{red}{lead.}\end{small}}
+\def\@partner{\begin{small}\textcolor{blue}{part.}\end{small}}
+\def\@IRISA{\ifx\IRISA\disable{}\else\ifx\IRISA\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@CITI{\ifx\CITI\disable{}\else\ifx\CITI\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@ALTERA{\ifx\ALTERA\disable{}\else\ifx\ALTERA\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@XILINX{\ifx\XILINX\disable{}\else\ifx\ALTERA\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{\@partner}\else{\@leader}\fi\fi}%
+\def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{\@partner}\else{\@leader}\fi\fi}%
+\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|}\hline
+\Sirisa  & \Sciti  & \Slip  & \Stima  & \Subs  & \Supmc  & \Saltera & \Sxilinx & \Sbull  & \Sthales & \Szied \\\hline
+\@IRISA  & \@CITI  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@ALTERA & \@XILINX & \@BULL  & \@THALES & \@ZIED \\\hline
 \end{tabular}\par
 }

anr/anr.tex

@@ -31 +31 @@
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\def\coussy{Philippe Coussy\xspace}
-\def\irisa{IRI\xspace}
-\def\citi{CITI\xspace}
-\def\lip{LIP\xspace}
-\def\tima{TIMA\xspace}
-\def\ubs{UBS\xspace}    % LAB-STICC
-\def\upmc{LIP6\xspace}
-\def\altera{ALTERA\xspace}
-\def\xilinx{XILINX\xspace}
-\def\bull{BULL\xspace}
-\def\thales{THALES\xspace}
-\def\zied{ZIED\xspace}
+\def\Sformat#1{\begin{small}\textsc{#1}\end{small}}
+\def\irisa{irisa\xspace}    \def\Sirisa{\Sformat{IRI}\xspace}
+\def\citi{CITI\xspace}      \def\Sciti{\Sformat{CITI}\xspace}
+\def\lip{LIP\xspace}        \def\Slip{\Sformat{LIP}\xspace}
+\def\tima{TIMA\xspace}      \def\Stima{\Sformat{TIMA}\xspace}
+\def\ubs{UBS\xspace}        \def\Subs{\Sformat{UBS}\xspace}
+\def\upmc{LIP6\xspace}      \def\Supmc{\Sformat{LIP6}\xspace}
+\def\altera{ALTERA\xspace}  \def\Saltera{\Sformat{ALTE}\xspace}
+\def\xilinx{XILINX\xspace}  \def\Sxilinx{\Sformat{XILX}\xspace}
+\def\bull{BULL\xspace}      \def\Sbull{\Sformat{BULL}\xspace}
+\def\thales{THALES\xspace}  \def\Sthales{\Sformat{THAL}\xspace}
+\def\zied{FLEXRAC\xspace}   \def\Szied{\Sformat{FLEX}\xspace}
 
 \def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
@@ -49 +49 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \def\ST{sub-task\xspace}
+\def\STs{sub-tasks\xspace}
 % FIXME \def\taskresponsable#1#2#3{\ifvmode\else\\\fi
 % FIXME The coordinator of this task is #1 member of #2.
@@ -210 +211 @@
 
 \subsubsection{Task 3: \textit{HAS front-end}}
-%\input{task-3}
+\input{task-3}
 
 \subsubsection{Task 4: \textit{HAS back-end}}
-%\input{task-4}
+\input{task-4}
 
 \subsubsection{Task 5: \textit{Communication between PC \& FPGA-SoC}}

anr/task-0.tex

@@ -19 +19 @@
 \end{objectif}
 %
-\begin{workpackage}{T0}
-\item This \ST consists of the writing of the consortium agreement and of having the patners to sign it.
+\begin{workpackage}{D0}
+\item This \ST consists of the writing of the consortium agreement and of having the
+    patners to sign it.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\upmc}{Consortium agreement establishment} A document signed by all the partners.
+    \item{-VF}{0}{6}{d}{\upmc}{Consortium agreement establishment} A document signed by
+        all the partners.
     \end{livrable}
-\item This \ST consists of the managment of deliverable.
+\item This \ST consists of the managment of deliverables.
     \begin{livrable}
     \item{-1-VF}{0}{12}{d}{\upmc}{First progress report}
@@ -31 +33 @@
     \end{livrable}
 \item This \ST consists of the set up of the web site and iof its managment.
-Deliverables:
     \begin{livrable}
     \item{-VF}{0}{6}{}{\upmc}{Web site setting}

anr/task-1.tex

@@ -11 +11 @@
 \end{objectif}
 %
-\begin{workpackage}{T1}
+\begin{workpackage}{D1}
 \item This \ST specifies COACH for the system designer. At this
     level COACH is a black box. The deliverable is a document allowing the system

anr/task-2.tex

@@ -22 +22 @@
 \end{objectif}
 %
-\begin{workpackage}{T2}
+\begin{workpackage}{D2}
 \item This \ST corresponds to the Coach System Generator (DSG) software.
     \begin{livrable}

anr/task-3.tex

@@ -13 +13 @@
     \mustbecompleted{FIXME:IRISA ........}
     \begin{livrable}
-        \item{-V1}{0}{18}{d}{\irisa}{Intégration manuelle des motifs} \mustbecompleted
-        \item{-VF}{18}{24}{d}{\irisa}{Intégration manuelle des motifs} \mustbecompleted
+        \item{-V1}{0}{18}{d}{\irisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
+        \item{-VF}{18}{24}{d}{\irisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
     \end{livrable}
 \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
     \begin{livrable}
-        \item{-V1}{0}{18}{d}{\irisa}{Intégration manuelle des motifs} \mustbecompleted
+        \item{-V1}{0}{18}{d}{\irisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
     \end{livrable}
 \end{workpackage}

anr/task-4.tex

@@ -69 +69 @@
     synthesis.
     \begin{livrable}
-    \item{-V1}{0}{6}{d}{\umpc}{frequency calibration} A document describing the set up of
+    \item{-V1}{0}{6}{d}{\upmc}{frequency calibration} A document describing the set up of
         the coprocessor frequency calibration.
-    \item{-V2}{6}{12}{x}{\umpc}{frequency calibration} A VHDL description of hardware
+    \item{-V2}{6}{12}{x}{\upmc}{frequency calibration} A VHDL description of hardware
         added to the coprocessor to enable the calibration.
-    \item{-V3}{12}{20}{x}{\umpc}{frequency calibration} The frequency calibration software
+    \item{-V3}{12}{20}{x}{\upmc}{frequency calibration} The frequency calibration software
         consists of a driver in the FPGA-SoC operating system and of a control software on
         a PC.

anr/task-5.tex

@@ -24 +24 @@
 \end{objectif}
 %
-\begin{workpackage}{T5}
+\begin{workpackage}{D5}
 \item This \ST is the definition of the communication schems as a software API
     (Application Programing Interface) between the application part running on the PC and
     the application part running on the FPGA-SoC.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\upmc}{HPC communication API} User refernce manual describing the API.
+    \item{-VF}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
     \end{livrable}
 \item This \ST aims with the application partitioning help. It is a library implementing
     the communication API with features to profile the application partionning.
     \begin{livrable}
-    \item{-VF}{0}{12}{x}{\upmc}{HPC partionning help} A library.
+    \item{-VF}{0}{12}{x}{\Supmc}{HPC partionning help} A library.
     \end{livrable}
 \item This \ST aims with the implementation of the communication API on the both sides (PC
     part and FPGA-SoC).
     \begin{livrable}
-    \item{-1-VF}{0}{21}{x}{\upmc}{HPC API for Linux PC} 
-    \item{-2-VF}{0}{21}{x}{\tima}{HPC API for DNA OS} 
-    \item{-3-VF}{0}{21}{x}{\upmc}{HPC API for Mutek OS} 
+    \item{-1-VF}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 
+    \item{-2-VF}{0}{21}{x}{\Stima}{HPC API for DNA OS} 
+    \item{-3-VF}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 
     \end{livrable}
 \item This \ST aims with the implementation of hardware required by the COACH
     architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \item{-1-VF}{0}{21}{h}{\tima}{HPC hardwre \xilinx} A synthesizable VHDL description
+    \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardwre \xilinx} A synthesizable VHDL description
         of a PLB/VCI bridge.
-    \item{-1-VF}{0}{21}{h}{\altera}{HPC hardwre \altera} A synthesizable VHDL description
+    \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardwre \altera} A synthesizable VHDL description
         of a AVALON/VCI bridge.
     \end{livrable}
 \item This \ST aims with the dynamic reconfiguration of FPGA.
     \begin{livrable}
-    \item{-1-VF}{0}{30}{x}{\tima}{dynamic reconfiguration DNA drivers}
-    \item{-2-VF}{0}{30}{x}{\upmc}{dynamic reconfiguration mutek drivers}
-    \item{-3-VF}{0}{30}{x}{\upmc}{CSG support for dynamic reconfiguration}
-    \item{-3-VF}{0}{30}{x}{\tima}{PC support for dynamic reconfiguration}
+    \item{-1-VF}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
+    \item{-2-VF}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
+    \item{-3-VF}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
+    \item{-3-VF}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
+    \end{livrable}
+\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
+    with its PCI/X IP. These boards are dedicated to the COACH HPC development.
+    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
+    \begin{livrable}
+    \item{-VF}{0}{6}{x}{\Saltera}{HPC development boards}
     \end{livrable}
 \end{workpackage}

anr/task-6.tex

@@ -10 +10 @@
 \end{objectif}
 %
-\begin{workpackage}{T6}
+\begin{workpackage}{D6}
 \item This \ST is the reference demonstrator. It is a HPC application and so it covers
     in addition to HPC (task-5) both the system genration (task-2), the HAS (task-3) and (task-4).