Changeset 272 for anr


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Timestamp:
Feb 20, 2010, 5:00:49 PM (15 years ago)
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alain
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anr
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  • anr/coach_summary.txt

    r270 r272  
    1 The objective of COACH is to provide an integrated design flow, based on the
    2 SoCLib virtual prototyping infrastructure, and optimized for the design of
    3 multi-processors digital systems targeting FPGA devices.
    4 Such digital systems are generally integrated
    5 into one or several chips, and there are two types of applications:
    6 They can be embedded (autonomous) applications
    7 such as personal digital assistants (PDA), ambiant computing components,
    8 or wireless sensor networks (WSN).
    9 They can also be extension boards connected to a PC to accelerate a specific computation,
    10 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
     1The objective of COACH is to provide an integrated design flow, based on the SoCLib virtual prototyping infrastructure, and optimized for the design of multi-processors digital systems targeting FPGA devices.  Such digital systems are generally integrated into one or several chips, and there are two types of applications:
     2- They can be embedded (autonomous) applications such as personal digital assistants (PDA), ambiant computing components, or wireless sensor networks (WSN).
     3- They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
    114
    125The COACH project will provide three hardware architectural templates:
    136
    14     - A Neutral architectural template based on the SoCLib IP core library and the
    15       VCI/OCP communication infrastructure.
    16     - An Altera architectural template based on the Altera IP core library, the
    17       AVALON system bus and the NIOS processor.
    18     - A Xilinx architectural template based on the Xilinx IP core library, the PLB
    19       system bus and the Microblaze processor.
     7    - A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
     8    - An Altera architectural template based on the Altera IP core library, the AVALON system bus and the NIOS processor.
     9    - A Xilinx architectural template based on the Xilinx IP core library, the PLB system bus and the Microblaze processor.
    2010
    21 The COACH design flow will be dedicated to system designers, and will as
    22 much as possible hide the hardware characteristics to the end-user.
    23 The specification of the application will be independant from the
    24 architectural template and the target FPGA device.
     11The COACH design flow will be dedicated to system designers, and will as much as possible hide the hardware characteristics to the end-user.  The specification of the application will be independant from the architectural template and the target FPGA device.
    2512
    26 To reach this ambitious goal, the project will rely on the experience and the
    27 complementariness of partners in the following domains:
    28 - Operating system and communication middleware (Tima, Lip6),
    29 - MPSoC architectures (Tima, Lab-Sticc, Lip6),
    30 - ASIP architectures (Inria/Cairn),
    31 - High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip).
     13To reach this ambitious goal, the project will rely on the experience and the complementariness of partners in the following domains:
     14- Operating system and communication middleware (Tima, Lip6)
     15- MPSoC architectures (Tima, Lab-Sticc, Lip6)
     16- ASIP architectures (Inria/Cairn)
     17- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip)
    3218
    33 The COACH project does not start from scratch.
    34 It stronly relies on the SoCLib virtual prototyping platform for prototyping,
    35 (DSX, component library), operating systems (MUTEKH, DNA/OS).
    36 It also leverages on  several existing technologies: the GAUT and UGH tools for HLS,
    37 the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations
    38 and on the Xilinx and Altera IP core libraries.
    39 Finally it will use the Xilinx and Altera logic and physical synthesis
    40 tools to generate the FPGA configuration bitstreams.
     19The COACH project does not start from scratch.  It stronly relies on the SoCLib virtual prototyping platform for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).  It also leverages on  several existing technologies: the GAUT and UGH tools for HLS, the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations, and the Xilinx and Altera IP core libraries.  Finally it will use the Xilinx and Altera logic and physical synthesis tools to generate the FPGA configuration bitstreams.
    4120
    42 Two major FPGA companies are involved in the project: Xilinx will contribute
    43 as a contractual partner providing documentation and manpower; Altera will contribute as
    44 a supporter, providing documentation and development boards. These two companies are strongly motivated
    45 to help the COACH project to generate efficient bitsreams for both FPGA families.
    46 The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide
    47 real use cases to benchmark the COACH design environment and to analyze the designer productivity
    48 improvements.
     21Two major FPGA companies are involved in the project: Xilinx will contribute as a contractual partner providing documentation and manpower; Altera will contribute as a supporter, providing documentation and development boards. These two companies are strongly motivated to help the COACH project to generate efficient bitsreams for both FPGA families.
    4922
    50 Following the general policy of the SoCLib platform, the COACH project will be an open
    51 infrastructure, available in the framework of the SoCLib server.
    52 The architectural templates, and the COACH software tools will be distributed under the
    53 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
    54 IP core library) will be freely available for non commercial use. For industrial exploitation
    55 the technology providers are ready to propose commercial licenses, directly to the end user,
    56 or through a third party.
     23The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide real use cases to benchmark the COACH design environment and to evaluate the designer productivity improvements.
    5724
    58 Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the
    59 "letters of interest", that have collected during the preparation of the project :
    60 - ADACSYS
    61 - MDS
    62 - INPIXAL
    63 - CAMKA System
    64 - ATEME
    65 - ALSIM
    66 - SILICOMP-AQL
    67 - ABOUND Logic
    68 - EADS-ASTRIUM
     25Following the general policy of the SoCLib platform, the COACH project will be an open infrastructure, available in the framework of the SoCLib server.  The architectural templates, and the COACH software tools will be distributed under the GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib IP core library) will be freely available for non commercial use. For industrial exploitation the technology providers are ready to propose commercial licenses, directly to the end user, or through a third party.
     26
     27Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the "letters of interest", that have collected during the preparation of the project :
     28    - ADACSYS
     29    - MDS
     30    - INPIXAL
     31    - CAMKA System
     32    - ATEME
     33    - ALSIM
     34    - SILICOMP-AQL
     35    - ABOUND Logic
     36    - EADS-ASTRIUM

  • anr/coach_summary_fr.txt

    r271 r272  
    1 L'objectif du projet COACH est de fournir un environnement complet de conception de
    2 systèmes digitaux multi-processeurs qui cible les circuits FPGA.
    3 Cet environnement sera basé sur la plate-forme SocLib de prototypage virtuel.
    4 Ces systèmes digitaux sont en général intégrés dans un ou plusieurs circuits
    5 et il y a principalement deux types d'applications:
    6 des applications autonomes comme celles embarquées dans des PDA, des composants
    7 domotiques ou des réseaux de capteurs;
    8 des cartes d'extension connectées à un PC pour du calcul haute performance
    9 (HPC) ou du traitement de signal haute performance (HSSP).
     1L'objectif du projet COACH est de fournir un environnement complet de conception de systèmes numériques multi-processeurs qui cible les circuits FPGA.  Cet environnement sera basé sur la plate-forme SocLib de prototypage virtuel. Ces systèmes numériques sont en général intégrés dans un ou plusieurs circuits et il y a principalement deux types d'applications:
     2    - des applications autonomes comme celles embarquées dans des PDA, des composants domotiques ou des réseaux de capteurs;
     3    - des cartes d'extension connectées à un PC pour du calcul haute performance (HPC) ou du traitement de signal haute performance (HSSP).
    104
    115Le projet COACH fournira trois patrons architecturaux.
    12     - Le patron architectural neutre qui sera basé sur la bibliotèque d'IP cores de
     6    - Le patron architectural neutre qui sera basé sur la bibliothèque d'IP cores de
    137          SocLib et sur l'infrastructure de communication VCI/OCP.
    148      VCI/OCP communication infrastructure.
    15     - Le patron architectural Altera qui sera basé sur la bibliotèque d'IP cores d'Altera,
     9    - Le patron architectural Altera qui sera basé sur la bibliothèque d'IP cores d'Altera,
    1610      le bus AVALON et le processeur NIOS.
    17     - Le patron architectural Xilinx qui sera basé sur la bibliotèque d'IP cores de Xilinx,
     11    - Le patron architectural Xilinx qui sera basé sur la bibliothèque d'IP cores de Xilinx,
    1812      le bus PLB et le processeur Microblaze.
    1913
    20 L'environnement de conception COACH sera conçu pour être utilisable pas un
    21 concepteur système. Pour cela il masquera aux utilisateurs les
    22 caractéristiques matérielles fines. De plus les descriptions des applications seront
    23 toalement indépendante des patrons architecturaux ainsi que du circuit FPGA visé.
     14L'environnement de conception COACH sera conçu pour être utilisable pas un concepteur système. Pour cela il masquera aux utilisateurs les caractéristiques matérielles fines. De plus les descriptions des applications seront totalement indépendante des patrons architecturaux ainsi que du circuit FPGA visé.
    2415
    25 Pour atteindre ces objectifs ambitieux, le projet repose sur la
    26 complémentarité et l'expérience des partenaires dans les domaines suivants:
    27   - système d'exploitation et middleware de communication (Tima, Lip6),
    28   - architectures MPSoC (Tima, Lab-Sticc, Lip6),
    29   - architectures ASIP (Inria/Cairn),
    30   - synthèse de haut niveau (Tima, Lab-Sticc, Lip6), et compilation (Ens-Lyon/Lip).
     16Pour atteindre ces objectifs ambitieux, le projet repose sur la complémentarité et l'expérience des partenaires dans les domaines suivants:
     17    - système d'exploitation et middleware de communication (Tima, Lip6),
     18    - architectures MPSoC (Tima, Lab-Sticc, Lip6),
     19    - architectures ASIP (Inria/Cairn),
     20    - synthèse de haut niveau (Tima, Lab-Sticc, Lip6), et compilation (Ens-Lyon/Lip).
    3121
    32 Le projet COACH ne demarre pas de rien mais s'appuie fortement sur la
    33 plate-forme SocLib (DSX, bibliotèque de composants), sur les systèmes
    34 d'exploitation (MUTEKH, DNA/OS).
    35 Il tirera également profit de plusieurs outils existants: les outils UGH et GAUT pour la
    36 synthèse de haut niveau, le projet ROMA pour les processeurs à instructions
    37 spécifiques (ASIP), les outils SYNTOL et BEE pour les transformations et
    38 l'analyse au niveau source, les bibliotèques de composants d'Altera et Xilinx.
    39 Enfin il utilisera les outils de synthèse logique et physique d'Altera et de
    40 Xilinx pour générer les bitstreams de configuration des FPGA.
     22Le projet COACH ne démarre pas de rien mais s'appuie fortement sur la plate-forme SocLib (DSX, bibliothèque de composants), sur les systèmes d'exploitation (MUTEKH, DNA/OS).  Il tirera également profit de plusieurs outils existants: les outils UGH et GAUT pour la synthèse de haut niveau, le projet ROMA pour les processeurs à instructions spécifiques (ASIP), les outils SYNTOL et BEE pour les transformations et l'analyse au niveau source, les bibliothèques de composants d'Altera et Xilinx.  Enfin il utilisera les outils de synthèse logique et physique d'Altera et de Xilinx pour générer les bitstreams de configuration des FPGA.
    4123
    42 Les deux plus grandes sociétés du domaine des FPGA prennent part à
    43 ce projet. Xilinx est partenaire du projet et fournira des ressources humaines
    44 et de la documentation. Altera supportera le projet en fournissant de la
    45 documentation et des cartes de développement.
    46 Ces deux sociétés sont très motivées à aider ce projet pour générer des
    47 bitstreams optimisés pour leurs circuits FPGA.
    48 Le rôle des partenaires industriels Bull, Thales, Navtel and Flexras est de
    49 fournir des applications industrielles pour évaluer les performances de
    50 l'environnement COACH ainsi que mesurer les gains de productivité obtenus.
     24Les deux plus grandes sociétés du domaine des FPGA sont impliquées dans le projet. Xilinx est partenaire du projet.  Altera contribue au projet en fournissant au projet de la documentation et des cartes de développement.  Ces deux sociétés sont très motivées à aider ce projet pour générer des bitstreams optimisés pour leurs circuits FPGA.
    5125
    52 Conformément à la politique générale de la plate-forme SocLib, le projet COACH
    53 sera sous licence libre, et disponible sur le serveur de la plate-forme SocLib.
    54 Les patrons architecturaux et les logiciels seront distribués sous la licence
    55 GPL, les modèles en VHDL synthétisable des composants du patron architectural
    56 neutre seront distribués aussi librement mais leur utilisation sera restreinte
    57 à un usage non commercial. Pour une utilisation commerciale de ces composants,
    58 les concepteurs de ces modèles fourniront des licences commerciales soit directement
    59 à l'utilisateur final soit à un tiers.
     26Le rôle des partenaires industriels Bull, Thales, Navtel and Flexras est de fournir des applications industrielles pour évaluer les performances de l'environnement COACH ainsi que mesurer les gains de productivité obtenus.
    6027
    61 Finalement, le projet COACH est supporté par un grand nombre de PME comme le
    62 que le montre les lettres de soutien qui ont été collectées.
    63 - ADACSYS
    64 - MDS
    65 - INPIXAL
    66 - CAMKA System
    67 - ATEME
    68 - ALSIM
    69 - SILICOMP-AQL
    70 - ABOUND Logic
    71 - EADS-ASTRIUM
     28Conformément à la politique générale de la plate-forme SocLib, le projet COACH sera sous licence libre, et disponible sur le serveur de la plate-forme SocLib.  Les patrons architecturaux et les logiciels seront distribués sous la licence GPL, les modèles en VHDL synthétisable des composants du patron architectural neutre seront distribués aussi librement mais leur utilisation sera restreinte à un usage non commercial. Pour une utilisation commerciale de ces composants, les concepteurs de ces modèles fourniront des licences commerciales soit directement à l'utilisateur final soit à une tierce partie.
     29
     30Finalement, le projet COACH est soutenu par un grand nombre de PME comme le montrent les lettres d'intérêt qui ont été collectées:
     31    - ADACSYS
     32    - MDS
     33    - INPIXAL
     34    - CAMKA System
     35    - ATEME
     36    - ALSIM
     37    - SILICOMP-AQL
     38    - ABOUND Logic
     39    - EADS-ASTRIUM

  • anr/section-3.2.tex

    r269 r272  
    4444\begin{description}
    4545\item[\textit{Design Space Exploration by Virtual Prototyping}]:
    46     The COACH environment will allow to easily map a parallel application described as a process
    47         network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
    48         permit to explore the design space by allowing system designer to select and
    49         parameterize the target architecture, and to define the best hardware/software
    50         partitioning of the application.
    51 \item[\textit{High-Level Synthesis}]:
    52     COACH will allow the automatic generation of hardware accelerators when required
     46        The COACH environment will allow to easily map a parallel application (formally described as
     47        an abstract network of process and communication channels) 
     48        COACH will permit the system designer to explore the design space, and to define the best
     49        hardware/software partitioning of the application.
     50\item[\textit{Integration of system level modeling and HLS tools}]:
     51        COACH will support the automated generation of hardware accelerators when required
    5352        by using High-Level Synthesis (HLS) tools. These HLS tools will be
    5453        fully integrated into a complete system-level design environment.
    5554        Moreover, COACH will support both data and control dominated applications,
    56     and the HLS tools of COACH will support a common language and coding style
     55        and the HLS tools of COACH will support a common language and coding style
    5756        to avoid re-engineering by the designer.
    58     COACH will provide a tool which will automatically explore the micro-architectural
     57        COACH will provide a tool which will automatically explore the micro-architectural
    5958        design space of coprocessor.
    6059\item[\textit{High-level code transformation}]:
    61     COACH will allow to optimize the memory usage, to enhance the parallelism through
     60        COACH will allow to optimize the memory usage, to enhance the parallelism through
    6261        loop transformations and parallelization. The challenge is to identify the coarse
    6362        grained parallelism and to generate,
    6463        from a sequential algorithm, application containing multiple communicating
    65         tasks. To this aim, one may adapt techniques which were developed in the 1990 for
     64        tasks. COACH will adapt techniques which were developed in the 1990 for
    6665        the construction of distributed programs. However, in the context of HLS, there are
    67         still several original problems to be solved, mainly to do with the construction of
    68         FIFO communication channels and with memory optimization.
    69         Additionnal preprocessing, source-level transformations, are thus
    70         required to improve the process.
    71         Particularly, this includes parallelism exposure and efficient memory mapping.
     66        several original problems to be solved, related to the  FIFO communication channels and with
     67        memory optimization.
    7268        COACH will support code transformation by providing a source to source C2C tool.
    73 \item[\textit{Hardware/Software communication middleware}]:
    74     COACH will implement an homogeneous HW/SW communication infrastructure and
    75     communication APIs (Application Programming Interface), that will be used for
    76     communications between software tasks running on embedded processors and
    77     dedicated hardware coprocessors. This will allow explore the design space by
    78         mapping the tasks of the application (described as a process network) on a
    79         shared-memory, MPSoC architecture.
     69\item[\textit{Unified Hardware/Software communication middleware}]:
     70        COACH will rely on he SoCLib experience to implement an unified hardware/software communication
     71        infrastructure and communication APIs (Application Programming Interface), to support 
     72        communications between software tasks running on embedded processors and dedicated
     73        hardware coprocessors. The main issue here is to support easy migration
     74        from a software implementation to an hardware implementation.
    8075\item[\textit{Processor customization}]:
    81 ASIP design will be addressed by the COACH project. COACH will allow system designers to explore
    82 the various level of interactions between the original CPU micro-architecture and its
    83   extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
    84  COACH will integrate ASIP design in a complete System-level design framework.
     76        ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project.
     77        COACH will allow system designers to explore the various level of interactions between
     78        the original CPU micro-architecture and its extension. It will also allow to retarget
     79        the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
     80        in a complete System-level design framework.
    8581\end{description}
    8682

  • anr/section-6.2.tex

    r140 r272  
    1 The COACH project will be coordinated by professor Alain Greiner from
     1The Coach project will be coordinated by the Professor Alain Greiner from
    22Université Pierre et Marie Curie.
    33Alain Greiner is the initiator and the main architect of the SoCLib project.
    4 This ANR platform for virtual prototyping of MPSoCs involved 6 industrial companies
    5 (including ST Microelectronics and \thales) and ten academic laboratories
    6 (5 of them are involved in the COACH project).
    7 The SoCLib project was managed by \thales, but the technical coordination has been done
    8 by Alain Greiner, who has a good experience in coordinating large technical projects
     4This ANR plat-form for virtual prototyping of MPSoCs involved 6 industrial companies
     5(including ST Microelectronics and Thales) and ten academic laboratories
     6(5 of them are involved in the Coach project).
     7The SoCLib project was managed by Thales, but the technical coordination has been done
     8by Alain Greiner, that has a good experience in coordinating large technical projects
    99in both industrial and academic contexts:
    10 %
     10
    1111\begin {itemize}
    1212\item
    … …  
    1616From 1986 to 1990, he worked for the french BULL company, as team leader,
    1717in charge of designing the Basic Processing Unit for the BULL
    18 DPS7000 computer, the most powerfull mainframe of the family.
     18DPS7000 computer, the most powerfull mainframe from the family.
    1919\item
    2020In 1990, Alain Greiner joined UPMC, as Professor and became the head of the
    21 MASI laboratory in 1994. From 2000, he was head of the Hardware Department
    22 of the LIP6 laboratory.
     21MASI laboratory in 1994.
    2322\item
    2423From 1990 to 2000, he was the leader of the the ALLIANCE project: This GPL based
    … …  
    2625in more than 200 universities worlwide, for education and research.
    2726This project obtained the Seymour Cray award in 1994.
     27\item
     28From 2000 to 2009, he was the head of the Hardware Department
     29of the LIP6 laboratory, and associate-director of the LIP6 laboratory.
    2830\end {itemize}
    2931
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