Changeset 277

Timestamp:

Nov 23, 2010, 6:02:16 PM (14 years ago)

Author:

coach

Message:

 

Location:

anr

Files:

• section-3.2.tex (modified) (2 diffs)
• section-4.1.tex (modified) (1 diff)

anr/section-3.2.tex

@@ -5 +5 @@
 either a HPC application (an application running on a PC that must be accelarate),
 or an embedded application (a standalone application),
-or a function of a larger design.}
+or a sub-system application of a larger design.}
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
@@ -35 +35 @@
 Once the SoC architecture is validated through performances analysis,
 COACH generates its bitstream in the case of HPC or embedded application,
-or its IP-XACT description for its integration in the case of a function.
+or its IP-XACT description for its integration in the case of a sub-system application.
 Both descriptions contain the hardware architecture and the application software.
 Furthermore in the HPC case, an executable containing the host application is

anr/section-4.1.tex

@@ -31 +31 @@
 hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger
 design or}
-as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
+as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
 launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the