Changeset 278


Ignore:
Timestamp:
Nov 24, 2010, 12:14:38 AM (14 years ago)
Author:
coach
Message:

Reduced the task number. Suppressed xilinx, navtel and flexra. Added mds.

Location:
anr
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • anr/Makefile

    r193 r278  
    11# set here all the sources files
    22# required to build anr.pdf
    3 SOURCES=        anr.tex anr.bib section-1.tex \
     3SOURCES=        anr.tex anr.bib anr.sty section-1.tex \
    44                        section-2.tex section-2.1.tex section-2.2.tex \
    55                        flow.pdf section-3.1.tex section-3.2.tex \
    … …  
    1212                        section-6.1.tex section-6.2.tex section-7.tex
    1313
    14 TABLES= table_upmc_full.tex table_upmc_short.tex \
    15                 table_tima_full.tex table_tima_short.tex \
     14TABLES= \
    1615                table_inria_cairn_full.tex table_inria_cairn_short.tex \
    1716                table_inria_compsys_full.tex table_inria_compsys_short.tex \
     17                table_tima_full.tex table_tima_short.tex \
    1818                table_ubs_full.tex table_ubs_short.tex \
    19                 table_xilinx_full.tex table_xilinx_short.tex \
     19                table_upmc_full.tex table_upmc_short.tex \
    2020                table_bull_full.tex table_bull_short.tex \
    2121                table_thales_full.tex table_thales_short.tex \
    22                 table_zied_full.tex table_zied_short.tex \
    23                 table_navtel_full.tex table_navtel_short.tex \
    24                 table_livrable_01.tex table_livrable_02.tex
     22                table_mds_full.tex table_mds_short.tex
    2523
    2624# PROGRAMS
    … …  
    3129        @$(FIG2DEV) -L pdf -p aaa $< $@
    3230
    33 anr.pdf: $(SOURCES) gantt1.tex gantt2.tex gantt $(TABLES)
     31anr.pdf: $(SOURCES) gantt
     32        touch gantt1.tex gantt2.tex  $(TABLES)
    3433        @echo "Generating pdf file"
    3534        @pdflatex anr.tex || true
    … …  
    4039        @grep ndefine anr.log
    4140
    42 anr.bbl:anr.aux anr.bib
    43         bibtex anr || true
    44 
    45 anr.aux gantt1.tex gantt2.tex $(TABLES):
    46         touch $@
    4741
    4842gantt: gantt.l

  • anr/anr.sty

    r263 r278  
    8585\let\UBS\disable%
    8686\let\UPMC\disable%
    87 \let\XILINX\disable%
    8887\let\BULL\disable%
    8988\let\THALES\disable%
    90 \let\NAVTEL\disable%
    91 \let\ZIED\disable%
     89\let\MDS\disable%
    9290}{%
    9391\ifx\ALL\enable%
    … …  
    9795  \ifx\TIMA\disable\let\TIMA\enable\fi%
    9896  \ifx\UBS\disable\let\UBS\enable\fi%
    99   \ifx\XILINX\disable\let\XILINX\enable\fi%
    10097  \ifx\BULL\disable\let\BULL\enable\fi%
    10198  \ifx\THALES\disable\let\THALES\enable\fi%
    102   \ifx\NAVTEL\disable\let\NAVTEL\enable\fi%
    103   \ifx\ZIED\disable\let\ZIED\enable\fi%
     99  \ifx\MDS\disable\let\MDS\enable\fi%
    104100\fi%
    105101\def\@leader{\begin{small}\textcolor{red}{lead.}\end{small}}
    … …  
    110106\def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{\@partner}\else{\@leader}\fi\fi}%
    111107\def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{\@partner}\else{\@leader}\fi\fi}%
    112 \def\@XILINX{\ifx\XILINX\disable{}\else\ifx\XILINX\enable{\@partner}\else{\@leader}\fi\fi}%
    113108\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{\@partner}\else{\@leader}\fi\fi}%
    114109\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{\@partner}\else{\@leader}\fi\fi}%
    115 \def\@NAVTEL{\ifx\NAVTEL\disable{}\else\ifx\NAVTEL\enable{\@partner}\else{\@leader}\fi\fi}%
    116 \def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{\@partner}\else{\@leader}\fi\fi}%
    117 \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|}\hline
    118 \Sirisa  & \Slip  & \Stima  & \Subs  & \Supmc  & \Sxilinx & \Sbull  & \Sthales & \Snavtel & \Szied \\\hline
    119 \@IRISA  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@XILINX & \@BULL  & \@THALES & \@NAVTEL & \@ZIED \\\hline
     110\def\@MDS{\ifx\MDS\disable{}\else\ifx\MDS\enable{\@partner}\else{\@leader}\fi\fi}%
     111\begin{tabular}{|c|c|c|c|c|c|c|c|}\hline
     112\Sirisa  & \Slip  & \Stima  & \Subs  & \Supmc  & \Smds & \Sbull  & \Sthales \\\hline
     113\@IRISA  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@MDS & \@BULL  & \@THALES \\\hline
    120114\end{tabular}\par
    121115}
    … …  
    136130 \begin{description}%
    137131 %\let\itemsave\item%
    138  \def\subtask{%
     132 \def\subtask##1{%
    139133    \global\advance\subtaskcnt1
    140134    \def\subtaskname{S\taskname-\the\subtaskcnt}%
    141     \item[\subtaskname]}}
     135    \item[\subtaskname: ##1]\mbox{}\\}}
    142136{\end{description}}
    143137
    … …  
    152146    \let\upmc\relax     \let\Supmc\relax
    153147    \let\altera\relax   \let\Saltera\relax
    154     \let\xilinx\relax   \let\Sxilinx\relax
    155148    \let\bull\relax     \let\Sbull\relax
    156149    \let\thales\relax   \let\Sthales\relax
    157     \let\zied\relax     \let\Szied\relax
    158     \let\navtel\relax   \let\Snavtel\relax
     150    \let\mds\relax      \let\Smds\relax
     151    \let\xilinx\relax
    159152    \immediate\write\ganttdata{%
    160153      T=\the\taskcnt\space S=\the\subtaskcnt\space%
    … …  
    240233    \let\upmc\relax     \let\Supmc\relax
    241234    \let\altera\relax   \let\Saltera\relax
    242     \let\xilinx\relax   \let\Sxilinx\relax
    243235    \let\bull\relax     \let\Sbull\relax
    244236    \let\thales\relax   \let\Sthales\relax
    245     \let\zied\relax     \let\Szied\relax
    246     \let\navtel\relax   \let\Snavtel\relax
     237    \let\mds\relax     \let\Smds\relax
    247238    \immediate\write\ganttdata{%
    248239      T=\the\taskcnt\space S=\the\subtaskcnt\space%

  • anr/anr.tex

    r276 r278  
    6565\def\zied{FLEXRAS\xspace}         \def\Szied{\Sformat{FLEX}\xspace}
    6666\def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace}
     67\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace}
    6768
    6869\def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
    … …  
    407408\bibliography{anr}
    408409
     410\end{document}
     411
    409412\newpage
    410413\section{Letters of interest}

  • anr/flow.fig

    r275 r278  
    20206 10800 2400 11272 3999
    21216 10879 2545 11194 3417
    22 4 1 0 50 -1 2 17 0.0000 4 205 173 11036 2763 P\001
    23 4 1 0 50 -1 2 17 0.0000 4 205 205 11036 2981 R\001
    24 4 1 0 50 -1 2 17 0.0000 4 205 236 11036 3199 O\001
    25 4 1 0 50 -1 2 17 0.0000 4 205 205 11035 3418 C\001
     224 1 0 50 -1 2 17 0.0000 4 195 180 11036 2763 P\001
     234 1 0 50 -1 2 17 0.0000 4 195 210 11036 2981 R\001
     244 1 0 50 -1 2 17 0.0000 4 195 225 11036 3199 O\001
     254 1 0 50 -1 2 17 0.0000 4 195 210 11035 3418 C\001
    2626-6
    27272 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
    … …  
    30306 11272 2400 11745 3999
    31316 11351 2545 11666 3199
    32 4 1 0 50 -1 2 17 0.0000 4 205 205 11509 2763 R\001
    33 4 1 0 50 -1 2 17 0.0000 4 205 205 11509 2981 A\001
    34 4 1 0 50 -1 2 17 0.0000 4 205 268 11509 3199 M\001
     324 1 0 50 -1 2 17 0.0000 4 195 210 11509 2763 R\001
     334 1 0 50 -1 2 17 0.0000 4 195 210 11509 2981 A\001
     344 1 0 50 -1 2 17 0.0000 4 195 270 11509 3199 M\001
    3535-6
    36362 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
    … …  
    40402 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
    4141         11824 2473 12139 2473 12139 3926 11824 3926 11824 2473
    42 4 1 0 50 -1 2 17 0.0000 4 205 110 11981 2763 I\001
    43 4 1 0 50 -1 2 17 0.0000 4 205 236 11981 2981 O\001
     424 1 0 50 -1 2 17 0.0000 4 195 105 11981 2763 I\001
     434 1 0 50 -1 2 17 0.0000 4 195 225 11981 2981 O\001
    4444-6
    45456 12217 2400 12690 3999
    46466 12296 2473 12611 3781
    47 4 1 0 50 -1 2 17 0.0000 4 205 173 12454 3127 P\001
    48 4 1 0 50 -1 2 17 0.0000 4 205 205 12454 3345 R\001
    49 4 1 0 50 -1 2 17 0.0000 4 205 236 12454 3563 O\001
    50 4 1 0 50 -1 2 17 0.0000 4 205 205 12453 3781 C\001
    51 4 1 0 50 -1 2 17 0.0000 4 205 236 12454 2909 O\001
    52 4 1 0 50 -1 2 17 0.0000 4 205 205 12454 2691 C\001
     474 1 0 50 -1 2 17 0.0000 4 195 180 12454 3127 P\001
     484 1 0 50 -1 2 17 0.0000 4 195 210 12454 3345 R\001
     494 1 0 50 -1 2 17 0.0000 4 195 225 12454 3563 O\001
     504 1 0 50 -1 2 17 0.0000 4 195 210 12453 3781 C\001
     514 1 0 50 -1 2 17 0.0000 4 195 225 12454 2909 O\001
     524 1 0 50 -1 2 17 0.0000 4 195 210 12454 2691 C\001
    5353-6
    54542 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
    … …  
    58582 2 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    5959         10879 4072 12611 4072 12611 4362 10879 4362 10879 4072
    60 4 1 0 50 -1 2 17 0.0000 4 205 567 11745 4290 BUS\001
     604 1 0 50 -1 2 17 0.0000 4 195 570 11745 4290 BUS\001
    6161-6
    6262-6
    … …  
    67674 1 0 50 -1 0 12 0.0000 4 195 2085 11790 5040 (bitstream or IP-XACT)\001
    68684 1 0 50 -1 2 16 0.0000 4 195 495 11820 4815 SoC\001
    69 -6
    70 6 1665 3300 3315 6107
    71 6 1665 3300 3315 4275
    72 2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    73          3240 4200 1740 4200 1740 3375 3240 3375 3240 4200
    74 4 0 0 50 -1 2 16 0.0000 4 195 585 2265 3750 HPC\001
    75 4 0 0 50 -1 2 16 0.0000 4 255 1335 1890 4050 application\001
    76 -6
    77 6 1725 5552 3255 6107
    78 2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    79          3240 6092 1740 6092 1740 5567 3240 5567 3240 6092
    80 4 1 0 50 -1 2 16 0.0000 4 195 1095 2490 5927 Function\001
    81 -6
    82 6 1665 4387 3315 5362
    83 2 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    84          3240 5287 1740 5287 1740 4462 3240 4462 3240 5287
    85 4 0 0 50 -1 2 16 0.0000 4 195 1245 1965 4837 Embedded\001
    86 4 0 0 50 -1 2 16 0.0000 4 255 1335 1890 5137 application\001
    87 -6
    8869-6
    89706 4275 2307 6675 4782
    … …  
    1631444 1 0 50 -1 2 16 0.0000 4 255 1140 8625 3630 Template\001
    164145-6
     1466 1650 3268 3300 4243
     1472 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
     148         3225 4168 1725 4168 1725 3343 3225 3343 3225 4168
     1494 0 0 50 -1 2 16 0.0000 4 195 585 2250 3718 HPC\001
     1504 0 0 50 -1 2 16 0.0000 4 255 1335 1875 4018 application\001
     151-6
     1526 1650 4355 3300 5330
     1532 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
     154         3225 5255 1725 5255 1725 4430 3225 4430 3225 5255
     1554 0 0 50 -1 2 16 0.0000 4 195 1245 1950 4805 Embedded\001
     1564 0 0 50 -1 2 16 0.0000 4 255 1335 1875 5105 application\001
     157-6
    1651582 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
    166159        1 1 2.00 60.00 120.00
    … …  
    1821752 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    183176         12855 1960 10650 1960 10650 1275 12855 1275 12855 1960
     1772 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
     178         3225 6300 1725 6300 1725 5535 3225 5535 3225 6300
    1841794 0 0 50 -1 2 16 0.0000 4 195 1305 11100 1650 Executable\001
    1851804 0 0 50 -1 2 16 0.0000 4 255 690 2250 675 Input\001
    … …  
    1891844 0 0 50 -1 2 16 0.0000 4 255 2535 4275 6300 Performance analysis\001
    1901854 0 0 50 -1 2 16 0.0000 4 255 2805 10350 6300 Running or Integration\001
     1864 1 0 50 -1 2 16 0.0000 4 255 1305 2475 5850 sub-system\001
     1874 1 0 50 -1 2 16 0.0000 4 255 1335 2475 6150 application\001

  • anr/gantt.l

    r251 r278  
    4747    { "ubs"    ,"ubs"    ,"table_ubs_full.tex"          ,"table_ubs_short.tex"    },
    4848    { "upmc"   ,"upmc"   ,"table_upmc_full.tex"         ,"table_upmc_short.tex"   },
    49     { "altera" ,"altera" ,"table_altera_full.tex"       ,"table_altera_short.tex" },
    50     { "xilinx" ,"xilinx" ,"table_xilinx_full.tex"       ,"table_xilinx_short.tex" },
    5149    { "bull"   ,"bull"   ,"table_bull_full.tex"         ,"table_bull_short.tex"   },
    5250    { "thales" ,"thales" ,"table_thales_full.tex"       ,"table_thales_short.tex" },
    53     { "zied"   ,"zied"   ,"table_zied_full.tex"         ,"table_zied_short.tex"   },
    54     { "navtel" ,"navtel" ,"table_navtel_full.tex"       ,"table_navtel_short.tex" },
     51    { "mds"    ,"mds"    ,"table_mds_full.tex"          ,"table_mds_short.tex"   },
    5552    { 0        ,0        ,0                             ,0                        },
    5653};
    … …  
    862859int main()
    863860{
    864     int tnplus[10] =  { 1, 2, 3, 4, 8, -1 };
    865     int tnmoins[10] = { 1, 2, 3, 4, 8, -1 };
     861    int tnplus[10] =  { 1, 2, 3, 4, 5, 6, -1 };
     862    int tnmoins[10] = { 1, 2, 3, 4, 5, 6, -1 };
    866863
    867864    yylex();
    … …  
    876873    prepare3(curr);
    877874    do_partner_table_full(1);  do_partner_table_short(1);
    878     do_partner_table_full(2);  do_partner_table_short(3);
     875    do_partner_table_full(2);  do_partner_table_short(2);
    879876    do_partner_table_full(3);  do_partner_table_short(3);
    880877    do_partner_table_full(4);  do_partner_table_short(4);
    881878    do_partner_table_full(5);  do_partner_table_short(5);
     879    do_partner_table_full(6);  do_partner_table_short(6);
    882880    do_partner_table_full(7);  do_partner_table_short(7);
    883881    do_partner_table_full(8);  do_partner_table_short(8);
    884     do_partner_table_full(9);  do_partner_table_short(9);
    885     do_partner_table_full(10); do_partner_table_short(10);
    886     do_partner_table_full(11); do_partner_table_short(10);
    887882
    888883    curr = data_new(0,0);
    … …  
    891886    prepare2(curr);
    892887    prepare3(curr);
    893     do_livrable_tables(70);
     888    do_livrable_tables(40);
    894889    return 0;
    895890}

  • anr/section-4.4.tex

    r266 r278  
    1717\hspace*{-.4cm}%\vspace{-1.5cm}
    1818\input{gantt1.tex}
    19 \caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 and task-8)}
     19\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)}
    2020\end{figure}
    2121
    … …  
    2323\hspace*{-.4cm}%\vspace{-1.5cm}
    2424\input{gantt2.tex}
    25 \caption{\label{gantt2}Gantt diagram of deliverables (task-5, task-6 and task-7)}
     25\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)}
    2626\end{figure}
    2727
    … …  
    7474%       Our experience with UGH and GAUT give us confidence in the succes of this
    7575%       task.
    76 \item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC},
    77      {\csgXilinxSystemC})]
     76\item[Virtual prototyping of \altera \& \xilinx architectural templates (\novers{\csgImplementation})]
    7877     The SoCLib component library contains several SystemC models used for the virtual
    7978     prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).

  • anr/section-7.tex

    r268 r278  
    169169
    170170%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    171 \subsection{Partner 6: \xilinx}
    172 
     171\subsection{Partner 6: \mds}
     172
     173\begin{ADDEDENV}
    173174\begin{description}
    174175\item[Equipment]
    … …  
    178179  The man power detail in \hommemois by deliverables is given in
    179180  figure~\ref{table-livrables-1} and a sumary by task in the following table.
    180   \begin{center}\input{table_xilinx_short.tex}\end{center}
     181  \begin{center}\input{table_mds_short.tex}\end{center}
    181182\item[Subcontracting]
    182183  No subcontracting costs.
    … …  
    187188\item[Other working costs] none
    188189\end{description}
     190\end{ADDEDENV}
    189191
    190192%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    234236
    235237%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    236 \subsection{Partner 9: \zied}
    237 
    238 \begin{description}
    239 \item[Equipment]
    240     No equipement costs.
    241 \item[Personnel costs]
    242     The effort to define SoC architecture and adapt eFPGA interface to generate is
    243     estimated to 9.6 \hommemois.
    244     The effort to develop demonstrator and to extract eFPGA timining characteristics is
    245     estimated to 4.8 \hommemois.
    246     Finally we need one 3.6 man.month for the evaluation of the FLEXRAS solution.
    247     The table below summarizes the these manpower costs in \hommemois for the deliverables
    248     and by tasks.
    249     \begin{center}\input{table_zied_full.tex}\end{center}
    250 \item[Subcontracting]
    251     No subcontracting costs.
    252 \item[Travel]
    253     No travel costs.
    254 \item[Expenses for inward billing] none
    255 \item[Other working costs] none
    256 \end{description}
    257 
    258 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    259 \subsection{Partner 10: \navtel}
    260 
    261 \begin{description}
    262 \item[Equipment]
    263     Navtel will use FPGA board with ARM processors for the validation.
    264     The costs for depreciation of the board and the instrument of test
    265     are evaluated to 7\% of the total requested ANR funding.
    266 \item[Personnel costs]
    267     A permanent engineer will be assigned on average 1/3 time for
    268         all the duration of the project.
    269     The table below shows the estimated manpower cost in \hommemois for the deliverables
    270     and by tasks.
    271     \begin{center}\input{table_navtel_full.tex}\end{center}
    272 \item[Subcontracting]
    273     No subcontracting costs.
    274 \item[Travel]
    275     The travel costs are associated to meeting, plenaries as well as participation to
    276     conferences. The travel costs are estimated to 3 k\euro.
    277 \item[Expenses for inward billing] none
    278 \item[Other working costs] none
    279 \end{description}
    280238%
    281239\begin{landscape}
    … …  
    286244\begin{minipage}[b]{.47\linewidth}\center
    287245\input{table_inria_cairn_full.tex}\vspace{.5ex}\\  \irisa  \vspace{2.5ex}\\
    288 \input{table_xilinx_full.tex}\vspace{.5ex}\\       \xilinx\\
     246\input{table_mds_full.tex}\vspace{.5ex}\\       \mds \\
    289247\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center
    290248\input{table_tima_full.tex}\vspace{.5ex} \\ \tima

  • anr/task-0.tex

    r267 r278  
    11\begin{taskinfo}
    2 \let\UPMC\leader
     2\let\MDS\leader
    33\let\ALL\enable
    44\end{taskinfo}
    … …  
    2020%
    2121\begin{workpackage}
    22   \subtask This \ST consists in writing and ratifying the consortium agreement.
     22  \subtask{Consortium agreement} This \ST consists in writing and ratifying the consortium agreement.
    2323    \begin{livrable}
    2424      \CoutHorsD{0}{36}{\Subs}{project management}{1:1:1}
    25     \itemL{0}{6}{d}{\Supmc}{Consortium agreement}{1:0:0}
     25    \itemL{0}{6}{d}{\Smds}{Consortium agreement}{1:0:0}
    2626        A document describing the consortium agreement, signed by all the partners.
    2727    \end{livrable}
    28   \subtask This \ST concerns the global management of the deliverables and of the global
     28  \subtask{Global management} This \ST concerns the global management of the deliverables and of the global
    2929    organization of the project at all the levels.
    3030    \begin{livrable}
    31       \itemL{0}{36}{d}{\Supmc}{Global management}{1:1:1}
     31      \itemL{0}{36}{d}{\Smds}{Global management}{1:1:1}
    3232        Global management of the project at all the
    3333        levels: progress monitoring, record keeping, meeting organization, review
    3434        organization, the writing of the review reports.
    3535    \end{livrable}
    36   \subtask This \ST consists in managing the project at the partner level.
     36  \subtask{Partner level management} This \ST consists in managing the project at the partner level.
    3737    It includes mainly the progress monitoring, the record keeping the participation to the
    3838    project meetings and the communication with the project leader and the other partners.
    … …  
    4141      \CoutHorsD{0}{36}{\Stima}{project management}{1:1:1}
    4242    \end{livrable}
    43   \subtask This \ST consists firstly in the building, and next in the administration and the
    44   maintenance of the development and dissemination infrastructure. It is also in charge of
     43  \subtask{Setup of dissemination infrastructure}
     44    This \ST consists firstly in the building, and next in the administration and the
     45    maintenance of the development and dissemination infrastructure. It is also in charge of
    4546    the COACH releases distribution.
    4647    \begin{livrable}

  • anr/task-1.tex

    r244 r278  
    1212%
    1313\begin{workpackage}
    14 \subtask This \ST specifies the COACH environment for the system designer. At this
    15     level the COACH framework is a black box. The deliverables are documents
    16     specifying: how to feed COACH (the inputs), how to use COACH (the design flow),
     14\subtask{Specification of the COACH environment}
     15    This \ST specifies the COACH environment for the system designer. In this
     16    \ST the COACH framework is a black box. The deliverables are documents
     17    specifying: how to feed COACH (the inputs), how to use COACH (use model),
    1718    what is generated (the outputs).
    1819    %(definition of the generic architecture of the
    … …  
    2223    \itemV{0}{6}{d}{\Supmc}{COACH specification} \setMacroInAuxFile{specGenManualI}
    2324        The first version of the COACH specification.
    24         This document contains the general description of the framework, the design flow and the
     25        This document contains the general description of the framework, the use model and the
    2526        description of the architectural templates.
    2627        It refers to the HAS specification (deliverable {\specHasManual}) and
    … …  
    5051            feed-backs of the demonstrator \STs.
    5152    \end{livrable}
    52 \subtask This \ST specifies the software COACH structure. The deliverable is a
     53\subtask{Internal software structure}
     54    This \ST specifies the COACH software structure. The deliverable is a
    5355    document listing all the COACH software components and how they cooperate.
    5456    \begin{livrable}
    … …  
    5759        Description of the software list and the data flow among the tools.
    5860    \end{livrable}
    59 \subtask This \ST specifies the \xcoach and the \xcoachplus formats.
     61\subtask{\xcoach format}
     62    This \ST specifies the \xcoach and the \xcoachplus formats.
    6063    \begin{livrable}
    6164    \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification}
    … …  
    7477    \itemV{6}{12}{x}{\Subs}{First release of C2X}
    7578        \setMacroInAuxFile{specXcoachToCAI}
    76         A GCC plugin C2X that generates a \xcoach description
     79        This delivrable groups 2 tools.
     80        The first one C2X is a GCC plugin that generates a \xcoach description
    7781        (defined in {\specXcoachDocI} deliverable) from a C/C++ task description
    7882        (defined in {\specHasManual} deliverable).
    79     \itemL{12}{18}{x}{\Subs}{C2X tool}{2:1:0}
     83        The second one X2C regenerates a C description from a \xcoach
     84        description.
     85        % TACHE INCLUSE mais non decrite;  Specification of the GCC driver tool.
     86    \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0}
    8087        \setMacroInAuxFile{specXcoachToCA}
    81          An updated version of C2X (\specXcoachToCAI) which supports the \xcoach format defined
     88         An updated version of C2X and X2C (\specXcoachToCAI) which supports the \xcoach format defined
    8289        in the {\specXcoachDoc} deliverable and the HAS input format defined in the {\specHasManual}
    8390        deliverable.
    84     \itemV{7}{12}{x}{\Subs}{First release of X2C}
    85         \setMacroInAuxFile{specXcoachToCBI}
    86         This second tool X2C regenerates a C description from a \xcoach
    87         description.
    88     \itemL{12}{18}{x}{\Subs}{X2C tool}{2:1:0}
    89         \setMacroInAuxFile{specXcoachToCB}
    90         The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined
    91         in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual}
    92         deliverable.
     91%    \itemV{7}{12}{x}{\Subs}{First release of X2C}
     92%        \setMacroInAuxFile{specXcoachToCBI}
     93%        This second tool X2C regenerates a C description from a \xcoach
     94%        description.
     95%    \itemL{12}{18}{x}{\Subs}{X2C tool}{2:1:0}
     96%        \setMacroInAuxFile{specXcoachToCB}
     97%        The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined
     98%        in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual}
     99%        deliverable.
    93100    \itemV{12}{18}{x}{\Supmc}{First release of X2SC}
    94101        \setMacroInAuxFile{specXcoachToSystemCI}
    … …  
    106113        Final release of the former software (\specXcoachToVhdlI) and integration
    107114        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
    108     \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
    109         \setMacroInAuxFile{specXilinxOptimization}
    110         This deliverable consists in optimizing the VHDL generated from \xcoachplus format
    111         (deliverable \novers{\specXcoachToVhdl}) for the \xilinx RTL synthesis tools.
    112         \ubs will provide several examples of VHDL source files generated from \xcoachplus,
    113         with explanations about generation process of main data structures used in VHDL sources,
    114         \xilinx will provide back a documentation listing that proposes VHDL generation enhancements.
    115115    \end{livrable}
    116116   
    117 \subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
    118     \begin{livrable}
    119     \itemL{0}{3}{d}{\Subs}{GCC driver specification}{1:0:0}
    120         Specification of the GCC driver tool.
    121     \itemV{3}{9}{x}{\Subs}{GCC driver}
    122         First release of the GCC driver tool.
    123         %en T0+18 car va peut etre evoluer en fonction du DSE µ-archi
    124     \itemL{9}{12}{x}{\Subs}{GCC driver}{3:0:0}
    125         Final release of the GCC driver tool.
    126     \end{livrable}
     117% TACHE INCLUSE SANS X2C & C2X
     118%\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
     119%    \begin{livrable}
     120%    \itemL{0}{3}{d}{\Subs}{GCC driver specification}{1:0:0}
     121%        Specification of the GCC driver tool.
     122%    \itemV{3}{9}{x}{\Subs}{GCC driver}
     123%        First release of the GCC driver tool.
     124%    %en T0+18 car va peut etre evoluer en fonction du DSE µ-archi
     125%    \itemL{9}{12}{x}{\Subs}{GCC driver}{3:0:0}
     126%        Final release of the GCC driver tool.
     127%    \end{livrable}
    127128
    128 \subtask Backend HLS tools use a characterized macro-cell library to build the
     129\subtask{Tool for cell library creation}
     130    Backend HLS tools use a characterized macro-cell library to build the
    129131    micro-architecture of a coprocessor. The characterisation of a cell depends
    130132    on the target device. The role of this \ST is to define the macro-cells and

  • anr/task-2.tex

    r253 r278  
    1212Its objective is to allow the system designer to explore the design space by
    1313quickly prototyping and then to automatically generate the FPGA-SoC systems.
    14 This task consists of
     14This task consists of:
    1515\begin{itemize}
    16 \item The development of all the missing components (SytemC models and/or synthesizable VHDL models
    17 of the IP-cores),
     16\item The development of the synthesizable models required for the connection of
     17the coprocessors on the platform bus (2 bridges).
    1818\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL),
    1919\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
    2020including its bitstream and software executable code,
    21 \item The specification of enhanced communication schemes and their sofware and hardware implementations.
    2221\end{itemize}
    23 This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
    24 to allow the demonstrators to start working.
    25 This release will include the standard communication schemes (based on SoCLib MWMR component)
     22A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
     23This release will include the standard communication schemes based on SoCLib MWMR component
    2624and support the neutral architectural template for prototyping and hardware generation.
    2725\end{objectif}
    2826%
    2927\begin{workpackage}
    30 \subtask This \ST corresponds to the COACH System Generator (CSG) software.
     28\subtask{Bridge implementation}
     29    This \ST deals with the development of the synthesizable models required for the connection of
     30    the coprocessors on the platform bus).
    3131    \begin{livrable}
    32     \itemV{0}{12}{x}{\Supmc}{CSG tool} \setMacroInAuxFile{csgCoachArch}
    33         The first software release of the CSG tool that will allow demonstrators to start
    34         working by using the neutral architectural template.
    35     \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
    36         The second release of CSG supports the \xilinx and \altera architectural
    37         templates and the enhanced communication system, but only for SystemC prototyping.
    38         This release integrates a first integration of HLS tools.
    39     \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
    40         This milestone extends CSG (\csgPrototypingOnly) to
    41         FPGA-SoC generation for the \xilinx and \altera architectural template.
    42     \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5}
    43         Final release of CSG.
     32    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
     33        \setMacroInAuxFile{hpcPlbBridge}
     34        The synthesizable VHDL description of a PLB/VCI bridge.
     35    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
     36        \setMacroInAuxFile{hpcAvalonBridge}
     37        The synthesizable VHDL description of an AVALON/VCI bridge.
    4438    \end{livrable}
    45 \subtask This \ST deals with the components of the architectural templates.
    46     \\
    47     For the neutral architectural template, it consists of the development of the VHDL
    48     synthesizable description of the missing communication components (MWMR)
    49         in order to support the process network communication model.
    50     Notice that the SystemC models
    51     comes from the SocLib ANR project, the processor with its cache comes from the TSAR
    52     ANR project.
    53     \\
    54     For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
    55     \begin{livrable}
    56     \itemL{0}{12}{h}{\Supmc}{Neutral architecture}{1:0:0}
    57         \setMacroInAuxFile{csgCoachArchTempl}
    58         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    59     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
    60        This deliverable consists in optimizing the VHDL descriptions of the components of
    61        the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
    62        \xilinx RTL synthesis tools.
    63        \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
    64        listing that proposes VHDL generation enhancements.
    65     \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
    66         \setMacroInAuxFile{csgXilinxSystemC}
    67         The SystemC simulation module of the MWMR component with a PLB bus interface plus
    68         the SystemC modules of the components of the \xilinx architectural template
    69         currently not available in the SocLib component library.
    70     \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
    71         The synthesizable VHDL description of the MWMR component corresponding to the
    72         SystemC module of the former deliverable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
    74        This deliverable consists in optimizing the MWMR VHDL description (deliverable
    75        \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
    76        \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
    77        listing that proposes VHDL generation enhancements.
    78     \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
    79         \setMacroInAuxFile{csgAlteraSystemC}
    80         The SystemC simulation module of the MWMR component with an AVALON bus interface plus
    81         the SystemC modules of the components of the \altera architectural template
    82         currently not available in the SocLib component library.
    83     \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
    84         The synthesizable VHDL description of the MWMR component corresponding to the
    85         SystemC module of the former deliverable (\csgAlteraSystemC);
    86     \itemL{6}{12}{d}{\Subs}{Communication adapter spec.}{1:0:0}
    87        \setMacroInAuxFile{gautCOMMoptimization}
    88        Specification of an optimized communication adapter (space and time) component to handle data interleaving.
    89        This evolution aims to solve out of order communication weakness of the classical MWMR.
    90     \itemV{12}{24}{x}{\Subs}{Communication adapter}{0:6:0}
    91        First release of the tool that generates the VHDL description of the optimized communication adapter
    92        and its corresponding SystemC module.
    93     \itemL{24}{30}{x}{\Subs}{Comm. adapter generator}{0:6:3}
    94        Final release of the tool that generates the VHDL description of the optimized
    95        communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
    97        This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    98        \novers{\gautCOMMoptimization}).
    99        \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
    100        listing that proposes VHDL generation enhancements.
    101     \end{livrable}
    102 \subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
    103     system and the development of drivers for the hardware architectural templates
    104     and enhanced communication schemes defined in \novers{\specCsgManual} deliverable.
     39\subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating
     40    system and the development of drivers for the hardware architectural templates.
    10541    For the \altera and \xilinx architectural templates, the OSs must also be ported on
    10642    the NIOS2 and MICROBLAZE processors.
    10743    \begin{livrable}
    108     \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
    109         The drivers required for the first CSG milestone (deliverable \csgCoachArch).
    110     \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
    111         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    112     \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
    113         Final release of the MUTEKH OS drivers.
    114     \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
    115         Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
     44%IVG    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
     45%IVG        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
     46%IVG    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
     47%IVG        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     48%IVG    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
     49%IVG        Final release of the MUTEKH OS drivers.
     50%IVG    \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
     51%IVG        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    11652    \itemV{6}{8}{x}{\Stima}{DNA OS}
    117         The drivers required for the first CSG milestone (deliverable \csgCoachArch).
     53        The drivers required for the first CSG milestone.
    11854    \itemV{8}{18}{x}{\Stima}{DNA 0S}
    119         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     55        The drivers required for the second CSG milestone.
    12056    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
    12157        Final release of the DNA OS drivers.
    … …  
    12359        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    12460    \end{livrable}
     61%
     62\subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software.
     63    \begin{livrable}
     64    \itemV{0}{12}{x}{\Supmc}{CSG tool}
     65        The first software release of the CSG tool that will allow demonstrators to start
     66        working by using the neutral architectural template only for SystemC.
     67    \itemV{12}{18}{x}{\Supmc}{CSG}
     68        The second release of CSG integrates the VHDL driver for the neutral
     69        architectural template, and an integration of an HLS tools
     70        but only for SystemC prototyping.
     71    \itemV{18}{24}{x}{\Supmc}{CSG}
     72        This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template.
     73    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation}
     74        Final release of CSG enhanced by the demonstrator's feedback.
     75    \end{livrable}
    12576\end{workpackage}

  • anr/task-3.tex

    r267 r278  
    2121%
    2222\begin{workpackage}
    23   \subtask This sub-task aims at providing compiler support for custom instructions
     23  \subtask{ASIP compiler}
     24  This sub-task aims at providing compiler support for custom instructions
    2425  within the HAS front-end. It will take as input the COACH intermediate
    2526  representation, and will output an annotated COACH IR containing the custom
    … …  
    3637    \end{livrable}
    3738 
    38  \subtask In this sub-task, we provide micro-architectural template models for the two target
     39 \subtask{Micro-architectural template models for ASIP}
     40 In this sub-task, we provide micro-architectural template models for the two target
    3941 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow.
    4042 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
    … …  
    4648      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
    4749      its instruction set extensions}
    48       \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
    49           { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
    50           already available from \altera}
    5150      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
    5251      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
    … …  
    5958    \end{livrable}
    6059
    61   \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.
    62 
     60 \subtask{Parallelism optimization}
     61  Extraction of parallelism in polyhedral loops and conversion into a process network.
    6362   \begin{livrable}
    6463    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}

  • anr/task-4.tex

    r267 r278  
    99The objectives of this task are to provide the two HAS back-ends of the COACH project and
    1010a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required
    11 by the processors and the system BUS.
    12 %pourquoi en majuscule?
     11by the processors and the system bus.
    1312\\
    1413The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an
    … …  
    2221UGH. These tools are complementary and not in competition because they cover respectively
    2322data and control dominated designs.
    24 The organization of the task is firstly to quickly integrate the existing HLS to the COACH
    25 framework. Secondly these tools will be improved to allows to treat data dominated application
    26 with a few control for GAUT and control dominated application with a few data processing
    27 for UGH. This will enlarge the domain the HLS can cover which is a strong limitation of the
    28 tools currently avilable \cite{HLSBOOK} \cite{IEEEDT} \cite{CATRENE}.
    2923\end{objectif}
    3024
    31 %FIXMA == {il faudrait fusionner les taches ST5-1 et ST5-2, non ???}
    3225\begin{workpackage}
    33 \subtask The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
    34     consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
    35     them by \xcoach and \xcoachplus drivers i.e. C2X, X2SC and X2VHDL.
     26\subtask{Making HAS back-end to read \xcoach format}
     27    The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework.
     28    by implementing the mechanism to read \xcoach format.
    3629    \begin{livrable}
    3730    \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0}
    3831        Release of the UGH software that reads \xcoach format.
    39     \itemV{12}{18}{x}{\Supmc}{UGH integration}
    40         Release of the UGH software that writes \xcoachplus format.
    41     \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0}
    42         Final release of the UGH software.
    43     \end{livrable}
    44 \subtask The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
    45     consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
    46     them by \xcoach and \xcoachplus drivers.
    47     \begin{livrable}
    4832    \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0}
    4933        Release of the GAUT software that is able to read \xcoach format.
     34    \end{livrable}
     35%
     36\subtask{Making HAS back-end to write \xcoachplus format}
     37    The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework.
     38    by implementing the mechanism to write \xcoachplus format.
     39    \begin{livrable}
     40    \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0}
     41        Release of the UGH software that writes \xcoachplus format.
    5042    \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0}
    5143        Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format.
    52     %\itemL{18}{33}{x}{\Subs}{Final release of GAUT}{0:1:6}
    53      %   Final release of the GAUT software.
    5444    \end{livrable}
    55 \subtask The goal of this \ST is to improve the UGH and GAUT HLS tools.
    56     UGH and GAUT experimentations have shown respectively usefull enhancements.
    57     \begin{livrable}
    58     \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0}
    59         Release of the UGH software with support for treating automatically data dominated sections
    60         included into a control dominated application.
    61     \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6}
    62         Release of the UGH software able to generate a micro-architecture without the
    63         variable binding currently done by the designer.
    64     \itemL{12}{24}{x}{\Subs}{Release of GAUT with \ganttlf enhanced synthesis steps}{0:9:0}
    65         Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps.
    66     \itemL{24}{33}{x}{\Subs}{Release of GAUT supporting \ganttlf new const./obj.}{0:0:7}
    67         Release of the GAUT software that supports the \xcoach model during the binding and the scheduling steps
    68         and also supports new constraints and objectives.
    69     \itemV{18}{24}{d}{\Subs}{Micro-architecture Exploration}\setMacroInAuxFile{MAE}
    70         Specification of a Design Space Exploration framework for the HAS Back-end:
    71         The high level specification tools, such as GAUT, have to be able to use synthesis feed-back
    72         informations in order to explore the design space and to generate optimized architectures.
    73     \itemL{24}{36}{x}{\Subs}{Micro-architecture Exploration}{0:4:4}
    74         Release of the GAUT software that supports the features defined in \MAE
    75     \end{livrable}
    76 \subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
     45
     46\subtask{Coprocessor frequency adaptation}
     47    In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
    7748    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
    7849    guarantee that the micro-architectures they generate accurately respect this
    … …  
    8455    \begin{livrable}
    8556    \itemV{0}{12}{d}{\Supmc}{Frequency calibration}
    86         A document describing the set up of the coprocessor frequency calibration.:
     57        A document describing the set up of the coprocessor frequency calibration.
    8758    \itemV{12}{24}{x}{\Supmc}{Frequency calibration}
    8859        \setMacroInAuxFile{freqCalibrationVhdl}
    … …  
    9162        The frequency calibration software consists of a driver in the FPGA-SoC operating
    9263        system and of a control software.
    93     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5}
    94        This deliverable consists in optimizing the VHDL description provided in
    95        \novers{\freqCalibrationVhdl}.
    96        \upmc will provide the VHDL description, \xilinx will provide back a documentation
    97        listing that proposes VHDL generation enhancements.
    9864    \end{livrable}
    9965\end{workpackage}

  • anr/task-5.tex

    r237 r278  
    2020\item Implementing the communication scheme at all levels: partition help, software
    2121implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
    22 \item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
    23 to optimize FPGA ressource usage.
     22%\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
     23%to optimize FPGA ressource usage.
    2424\end{itemize}
    2525
    … …  
    3333%
    3434\begin{workpackage}
    35   \subtask
     35  \subtask{Implementation of API between PC and FPGA-SoC}
    3636    This \ST deals with the COACH HPC feature that consists in accelerating an existing
    37     apllication running on a PC by migrating critical parts into a SoC implemented on an
     37    application running on a PC by migrating critical parts into a SoC implemented on an
    3838    FPGA plugged to the PC PCI/X bus.
    3939    The main steps and components of this \ST are:
    … …  
    5454        \setMacroInAuxFile{hpcCommHelper}
    5555        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
    56         This library is dedicated to help the end-user to partition an applicattion for
    57         HPC.
     56        This library is dedicated to help the end-user to partition an application for HPC.
    5857      \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0}
    5958        \setMacroInAuxFile{hpcCommLinux}
    60         The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
    61         library and probably a LINUX module.
    62       \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
    63         \setMacroInAuxFile{hpcMutekDriver}
    64         The FPGA-SoC part of the communication API, a driver.
     59        The PC part of the HPC communication API that communicates with the FPGA-SOC, a
     60        library and a LINUX module.
     61%      \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
     62%        \setMacroInAuxFile{hpcMutekDriver}
     63%        The FPGA-SoC part of the communication API, a driver.
    6564      \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
    6665        \setMacroInAuxFile{hpcDnaDriver}
    67         Port of the {\hpcMutekDriver} driver on the DNA OS.
    68       \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
    69         Bug corrections and enhancements of communication middleware
    70         (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
    71         \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
     66        The FPGA-SoC part of the communication API.
     67%        Port of the {\hpcMutekDriver} driver on the DNA OS.
     68%      \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
     69%        Bug corrections and enhancements of communication middleware
     70%        (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
     71%        \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
    7272    \end{livrable}
    7373
    74 \subtask This \ST deals with the implementation of hardware and SystemC modules
     74\subtask{SystemC model of the PCI/X}
     75    This \ST deals with the implementation of hardware and SystemC modules
    7576    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
    7677    \begin{livrable}
    77     \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
    78         \setMacroInAuxFile{hpcPlbBridge}
    79         The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
    80     \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
    81         \setMacroInAuxFile{hpcAvalonBridge}
    82         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
     78% FIXME: moved to task 3 (CSG)
     79%    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
     80%        \setMacroInAuxFile{hpcPlbBridge}
     81%        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
     82%    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
     83%        \setMacroInAuxFile{hpcAvalonBridge}
     84%        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
    8385    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
    8486        The SystemC description of a component that generates PCI/X traffic. It is
    … …  
    8688    \end{livrable}
    8789
    88 \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
    89 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
    90     \begin{livrable}
    91     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
    92         Modification of the CSG software to support statically reconfigurable tasks.
    93     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
    94                 This livrable is a CSG module allowing to partition the task graph along
    95                 the dynamic partial reconfiguration regions. The resulting task-region assignement
    96                 is directly used for generation of bitstreams. The module also produces reconfiguration
    97                 management software to be run on the SoC-FPGA.
    98     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
    99         \setMacroInAuxFile{hpcDynconfDriver}
    100             The drivers required by the DNA OS in order to manage dynamic partial
    101         reconfiguration inside the SoC-FPGA.
    102     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
    103         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
    104     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
    105         Extension of the HPC partionning helper in order to integrate dynamic partial
    106         reconfiguration dedicated features (reconfiguration time of regions, variable
    107         number of coprocessors).
    108     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
    109         \xilinx will work with \tima in order to better take into account during
    110         partitioning decisions specific constraints due to partial reconfiguration process.
    111         The deliverable is a document describing the \xilinx specific constraints.
    112     \end{livrable}
    113 %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    114 %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
    115 %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    116 %   \begin{livrable}
    117 %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
    118 %   \end{livrable}
     90% \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
     91% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
     92%     \begin{livrable}
     93%     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
     94%         Modification of the CSG software to support statically reconfigurable tasks.
     95%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
     96%               This livrable is a CSG module allowing to partition the task graph along
     97%               the dynamic partial reconfiguration regions. The resulting task-region assignement
     98%               is directly used for generation of bitstreams. The module also produces reconfiguration
     99%               management software to be run on the SoC-FPGA.
     100%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
     101%         \setMacroInAuxFile{hpcDynconfDriver}
     102%           The drivers required by the DNA OS in order to manage dynamic partial
     103%         reconfiguration inside the SoC-FPGA.
     104%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
     105%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
     106%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
     107%         Extension of the HPC partionning helper in order to integrate dynamic partial
     108%         reconfiguration dedicated features (reconfiguration time of regions, variable
     109%         number of coprocessors).
     110%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
     111%         \xilinx will work with \tima in order to better take into account during
     112%         partitioning decisions specific constraints due to partial reconfiguration process.
     113%         The deliverable is a document describing the \xilinx specific constraints.
     114%     \end{livrable}
     115% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     116% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
     117% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
     118% %   \begin{livrable}
     119% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
     120% %   \end{livrable}
    119121\end{workpackage}

  • anr/task-6.tex

    r268 r278  
    1313%
    1414\begin{workpackage}
    15   \subtask
     15  \subtask{\bull HPC demonstrator}
    1616    The application that \bull proposes is HPC oriented.
    1717    The domain of the application is the treatment of medical images (image noise
    … …  
    3131    \end{livrable}
    3232
    33   \subtask
    34     The objective of this sub-task is to specify the THALES application and to develop the
     33  \subtask{\TRT Embedded SoC demonstrator}
     34    The objective of this sub-task is to specify the \TRT application and to develop the
    3535    high level code.  This application is in the domain of surveillance of critical
    3636    infrastructures. The objective is to detect and classify the presence of humans in the
    … …  
    5353        This deliverable is a document that specifies the application.
    5454      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0}
    55         This deliverable is the code of the application spcecified former
     55        This deliverable is the code of the application specified former
    5656        deliverable (\trtAppSpecification).
    5757    \end{livrable}
    5858
    59   \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
     59  \subtask{SPEAR-DE adaptation for COACH}
     60    \TRT will use its internal software environment tool SPEAR DE to describe the
    6061    application. The tool is able to partition and to generate the code for the target. \\
    6162    In this task, we will adapt SPEAR DE to generate the application description input of
    … …  
    6869    \end{livrable}
    6970
    70   \subtask
     71  \subtask{\mds use case}
     72    \mds will use .................
     73    \begin{livrable}
     74      \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0}
     75        \setMacroInAuxFile{trtSpearde}
     76        Adaptation of SPEAR-DE for COACH framework.
     77    \end{livrable}
     78
     79  \subtask{Evaluation report}
     80    % FIXME: AJOUTER une evaluation de BULL ET MDS
    7181    In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
    7282    its ability to generate a whole VHDL of an embedded system on FPGA for an application
    … …  
    8898    \end{livrable}
    8999
    90   \subtask FLEXRAS will design an application based on M-JPEG video standard.
    91         FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA).
    92     The architecture is composed essentially of a processor, a bus and several RAMs.
    93     The embedded FPGA is connected to the bus and communicates with the other components.
    94     The (eFPGA) works in 2 modes:
    95     \begin{description}
    96       \item[Slave mode]
    97         As a DMA, the processor will send the configuration bitstream
    98         stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
    99         writeable memory and is configured by the processor.
    100       \item[Master mode]
    101         Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
    102     \end{description}
    103       The top architecture of this SoC based-platform will be generated using COACH
    104       framework. The application that will be run on the SoC corresponds initially to a
    105       graph of software tasks. Critical tasks will be identified and transformed
    106       automatically to hardware tasks using COACH high level synthesis feature. While
    107       software tasks will be run on the processor, hardware ones will be mapped on eFPGA
    108       to take advantage of its optimized resources and parallelism. FLEXRAS provides all
    109       the flow from RTL synthesis to bitstream generation.
    110     \begin{livrable}
    111       \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
    112         FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
    113         generate the SoC architecture.
    114         This deliverable is a document that describes this architecture.
    115       \itemL{6}{18}{h}{\Szied}{eFPGA/VCI component}{3.6:3.6:0}
    116         FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
    117         This deliverable is a VHDL description.
    118 %      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
    119 %        Port of the bitstream loader to the MUTEKH operating system.
    120       \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
    121         \zied will propose to test COACH framework and the \zied architecture template
    122         throught an application based on M-JPEG video standard.
    123         This applicattion will containt 3 communicating tasks under the COACH format specified
    124         in {\novers{\specGenManual}} deliverable.
    125         The first one is a hardware task generated by the HAS tools and transformed into
    126         a bit stream by the \zied tools.
    127         The second is a bitstream loader that will load the bitstream of the first task on
    128         the eFPGA.
    129         The third is a software task that communicates with the hw task for testing it.
    130       \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
    131         This deliverable is a file under the format defined by the deliverable
    132         {\specMacroCell} that characterizes the eFPGA. This will allow the COACH HLS tools
    133         to take into account the eFPGA delays.
    134       \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
    135         This deliverable is a document that describes the tests, the validation and the
    136         evaluation of COACH with the \zied architecture and tools.
    137     \end{livrable}
    138 
    139   \subtask
    140   The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
    141   coupled module between %ARM
    142   a embedded processor and an FPGA both on a board.
    143   By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio
    144   through a polyphase resampler and one for an industrial control application through an embedded
    145   PID controller.
    146   The objective is to sequence the cores in realtime in FPGA using partial configuration methods
    147   proposed in the COACH project.
    148   This will allow us to gain experience on automatic multi core sequencing at system level. The
    149   specification for our first work package will concern this aspect.
    150 
    151   The ESC can function on different topologies: Single, parallel or Grid computing modes for
    152   industrial and scientific applications.
    153   %The ARM
    154   The processor and FPGA configuration also facilitate the co-simulation which allows to  gain
    155   time on the development and integration phase.
    156   The architecture consists of a wrapper that encapsules computing units depending on the
    157   application and a real time kernal for task switching and partial reconfiguration of FPGA
    158   on run time environment.
    159   \parlf
    160   To day \navtel develops these computing units manually.
    161   \navtel expects to benefit from the COACH project especially the HLS tools for
    162   generating the computing unit.
    163   \begin{livrable}
    164     \itemL{0}{6}{d}{\Snavtel}{\navtel \ganttlf demonstrator specification}{4:0:0}
    165         \setMacroInAuxFile{navtelSpecification}
    166         A document that will define the requirements for automatic RTL generation for
    167         signal processing units of our market sector such as digital communication,
    168         imaging and industrial control.
    169         This document will include the description of some already handmade processing units.
    170     \itemL{6}{18}{h}{\Snavtel}{\navtel \ganttlf wrapper adaptation}{1:1:0}
    171                 The adaptation of our wrapper to support coprocessor generated by COACH.
    172     \itemL{18}{36}{d}{\Snavtel}{\navtel evaluation}{0:2:4}
    173                 \navtel will test the COACH HLS tools on the processing units that are described
    174         in the {\navtelSpecification} deliverable.
    175                 A document will be written that describes the results obtained taking into
    176         account: 1) the performance in terms of space, 2) the performance in terms of
    177         time, 3) the friendlyness of the environment.
    178     \end{livrable}
    179100\end{workpackage}

  • anr/task-7.tex

    r267 r278  
    11\begin{taskinfo}
    2 \let\UPMC\leader
     2\let\MDS\leader
    33\let\ALL\enable
    44\end{taskinfo}
    … …  
    2020%
    2121\begin{workpackage}
    22   \subtask This \ST relates to the management of the WEB site and to the distribution of
     22  \subtask{\mustbecompleted{TITLE}} This \ST relates to the management of the WEB site and to the distribution of
    2323    the COACH releases.
    2424    \begin{livrable}
    … …  
    3838      \CoutHorsD{12}{36}{\Stima}{dissemination}{0:2:1}
    3939    \end{livrable}
    40   \subtask
     40  \subtask{\mustbecompleted{TITLE}}
    4141    \label{subtask-tutorial}
    4242    This \ST consists of making a COACH tutorial and to publish it on the public WEB
    … …  
    5959    \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1}
    6060        The final release of the tutorial.
    61     \itemL{30}{33}{d}{\Sxilinx}{\xilinx feedback}{0:0:0.5}
    62         \xilinx will check that the developped tutorial works well with \xilinx tools,
    63         and will propose corrections or enhancements if needed into a document.
    6461    \end{livrable}
    65   \subtask
     62  \subtask{\mustbecompleted{TITLE}} 
    6663    This \ST consists of making the COACH user reference manuals.
    6764    They will be published on the public WEB site.
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