- Timestamp:
- Nov 23, 2010, 6:02:16 PM (14 years ago)
- Location:
- anr
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/section-3.2.tex
r275 r277 5 5 either a HPC application (an application running on a PC that must be accelarate), 6 6 or an embedded application (a standalone application), 7 or a function of a larger design.}7 or a sub-system application of a larger design.} 8 8 \begin{figure}[hbtp]\leavevmode\center 9 9 \includegraphics[width=.8\linewidth]{flow} … … 35 35 Once the SoC architecture is validated through performances analysis, 36 36 COACH generates its bitstream in the case of HPC or embedded application, 37 or its IP-XACT description for its integration in the case of a function.37 or its IP-XACT description for its integration in the case of a sub-system application. 38 38 Both descriptions contain the hardware architecture and the application software. 39 39 Furthermore in the HPC case, an executable containing the host application is -
anr/section-4.1.tex
r275 r277 31 31 hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger 32 32 design or} 33 as a SystemC simulator (cycl aaccurate and/or TLM) to prototype and explore quickly the33 as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the 34 34 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and 35 35 launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the
Note: See TracChangeset
for help on using the changeset viewer.