Changeset 278 for anr/task-3.tex

Timestamp:

Nov 24, 2010, 12:14:38 AM (14 years ago)

Author:

coach

Message:

Reduced the task number. Suppressed xilinx, navtel and flexra. Added mds.

File:

• anr/task-3.tex (modified) (4 diffs)

anr/task-3.tex

@@ -21 +21 @@
 %
 \begin{workpackage}
-  \subtask This sub-task aims at providing compiler support for custom instructions 
+  \subtask{ASIP compiler}
+  This sub-task aims at providing compiler support for custom instructions 
   within the HAS front-end. It will take as input the COACH intermediate 
   representation, and will output an annotated COACH IR containing the custom
@@ -36 +37 @@
     \end{livrable}
  
- \subtask In this sub-task, we provide micro-architectural template models for the two target
+ \subtask{Micro-architectural template models for ASIP}
+ In this sub-task, we provide micro-architectural template models for the two target
  processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. 
  For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
@@ -46 +48 @@
       {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
-          { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
-          already available from \altera}
       \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
@@ -59 +58 @@
     \end{livrable}
 
-  \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.
-
+ \subtask{Parallelism optimization}
+  Extraction of parallelism in polyhedral loops and conversion into a process network.
    \begin{livrable}
     \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}