Changeset 278 for anr/task-6.tex

Timestamp:

Nov 24, 2010, 12:14:38 AM (14 years ago)

Author:

coach

Message:

Reduced the task number. Suppressed xilinx, navtel and flexra. Added mds.

File:

• anr/task-6.tex (modified) (5 diffs)

anr/task-6.tex

@@ -13 +13 @@
 %
 \begin{workpackage}
-  \subtask
+  \subtask{\bull HPC demonstrator}
     The application that \bull proposes is HPC oriented.
     The domain of the application is the treatment of medical images (image noise
@@ -31 +31 @@
     \end{livrable}
 
-  \subtask
-    The objective of this sub-task is to specify the THALES application and to develop the
+  \subtask{\TRT Embedded SoC demonstrator}
+    The objective of this sub-task is to specify the \TRT application and to develop the
     high level code.  This application is in the domain of surveillance of critical
     infrastructures. The objective is to detect and classify the presence of humans in the
@@ -53 +53 @@
         This deliverable is a document that specifies the application.
       \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0}
-        This deliverable is the code of the application spcecified former
+        This deliverable is the code of the application specified former
         deliverable (\trtAppSpecification).
     \end{livrable}
 
-  \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
+  \subtask{SPEAR-DE adaptation for COACH}
+    \TRT will use its internal software environment tool SPEAR DE to describe the
     application. The tool is able to partition and to generate the code for the target. \\
     In this task, we will adapt SPEAR DE to generate the application description input of
@@ -68 +69 @@
     \end{livrable}
 
-  \subtask 
+  \subtask{\mds use case}
+    \mds will use .................
+    \begin{livrable}
+      \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0}
+        \setMacroInAuxFile{trtSpearde}
+        Adaptation of SPEAR-DE for COACH framework.
+    \end{livrable}
+
+  \subtask{Evaluation report}
+    % FIXME: AJOUTER une evaluation de BULL ET MDS
     In this sub-task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
     its ability to generate a whole VHDL of an embedded system on FPGA for an application
@@ -88 +98 @@
     \end{livrable}
 
-  \subtask FLEXRAS will design an application based on M-JPEG video standard. 
-        FLEXRAS will propose a SoC architecture integrating an embedded FPGA (eFPGA).
-    The architecture is composed essentially of a processor, a bus and several RAMs.
-    The embedded FPGA is connected to the bus and communicates with the other components.
-    The (eFPGA) works in 2 modes:
-    \begin{description}
-      \item[Slave mode]
-        As a DMA, the processor will send the configuration bitstream
-        stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
-        writeable memory and is configured by the processor.
-      \item[Master mode]
-        Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
-    \end{description}
-      The top architecture of this SoC based-platform will be generated using COACH
-      framework. The application that will be run on the SoC corresponds initially to a
-      graph of software tasks. Critical tasks will be identified and transformed
-      automatically to hardware tasks using COACH high level synthesis feature. While
-      software tasks will be run on the processor, hardware ones will be mapped on eFPGA
-      to take advantage of its optimized resources and parallelism. FLEXRAS provides all
-      the flow from RTL synthesis to bitstream generation.
-    \begin{livrable}
-      \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
-        FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
-        generate the SoC architecture.
-        This deliverable is a document that describes this architecture.
-      \itemL{6}{18}{h}{\Szied}{eFPGA/VCI component}{3.6:3.6:0}
-        FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
-        This deliverable is a VHDL description.
-%      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
-%        Port of the bitstream loader to the MUTEKH operating system.
-      \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
-        \zied will propose to test COACH framework and the \zied architecture template
-        throught an application based on M-JPEG video standard.
-        This applicattion will containt 3 communicating tasks under the COACH format specified
-        in {\novers{\specGenManual}} deliverable.
-        The first one is a hardware task generated by the HAS tools and transformed into
-        a bit stream by the \zied tools.
-        The second is a bitstream loader that will load the bitstream of the first task on
-        the eFPGA.
-        The third is a software task that communicates with the hw task for testing it.
-      \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
-        This deliverable is a file under the format defined by the deliverable
-        {\specMacroCell} that characterizes the eFPGA. This will allow the COACH HLS tools
-        to take into account the eFPGA delays.
-      \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
-        This deliverable is a document that describes the tests, the validation and the
-        evaluation of COACH with the \zied architecture and tools.
-    \end{livrable}
-
-  \subtask
-  The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
-  coupled module between %ARM 
-  a embedded processor and an FPGA both on a board.
-  By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio 
-  through a polyphase resampler and one for an industrial control application through an embedded 
-  PID controller.
-  The objective is to sequence the cores in realtime in FPGA using partial configuration methods 
-  proposed in the COACH project. 
-  This will allow us to gain experience on automatic multi core sequencing at system level. The 
-  specification for our first work package will concern this aspect. 
-
-  The ESC can function on different topologies: Single, parallel or Grid computing modes for
-  industrial and scientific applications.
-  %The ARM
-  The processor and FPGA configuration also facilitate the co-simulation which allows to  gain
-  time on the development and integration phase.
-  The architecture consists of a wrapper that encapsules computing units depending on the
-  application and a real time kernal for task switching and partial reconfiguration of FPGA
-  on run time environment.
-  \parlf
-  To day \navtel develops these computing units manually.
-  \navtel expects to benefit from the COACH project especially the HLS tools for
-  generating the computing unit.
-  \begin{livrable}
-    \itemL{0}{6}{d}{\Snavtel}{\navtel \ganttlf demonstrator specification}{4:0:0}
-        \setMacroInAuxFile{navtelSpecification}
-        A document that will define the requirements for automatic RTL generation for
-        signal processing units of our market sector such as digital communication,
-        imaging and industrial control.
-        This document will include the description of some already handmade processing units.
-    \itemL{6}{18}{h}{\Snavtel}{\navtel \ganttlf wrapper adaptation}{1:1:0}
-                The adaptation of our wrapper to support coprocessor generated by COACH.
-    \itemL{18}{36}{d}{\Snavtel}{\navtel evaluation}{0:2:4}
-                \navtel will test the COACH HLS tools on the processing units that are described
-        in the {\navtelSpecification} deliverable.
-                A document will be written that describes the results obtained taking into
-        account: 1) the performance in terms of space, 2) the performance in terms of
-        time, 3) the friendlyness of the environment.
-    \end{livrable}
 \end{workpackage}