Changeset 278 for anr/task-5.tex


Ignore:
Timestamp:
Nov 24, 2010, 12:14:38 AM (14 years ago)
Author:
coach
Message:

Reduced the task number. Suppressed xilinx, navtel and flexra. Added mds.

File:
1 edited

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  • anr/task-5.tex

    r237 r278  
    2020\item Implementing the communication scheme at all levels: partition help, software
    2121implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
    22 \item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
    23 to optimize FPGA ressource usage.
     22%\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
     23%to optimize FPGA ressource usage.
    2424\end{itemize}
    2525
    … …  
    3333%
    3434\begin{workpackage}
    35   \subtask
     35  \subtask{Implementation of API between PC and FPGA-SoC}
    3636    This \ST deals with the COACH HPC feature that consists in accelerating an existing
    37     apllication running on a PC by migrating critical parts into a SoC implemented on an
     37    application running on a PC by migrating critical parts into a SoC implemented on an
    3838    FPGA plugged to the PC PCI/X bus.
    3939    The main steps and components of this \ST are:
    … …  
    5454        \setMacroInAuxFile{hpcCommHelper}
    5555        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
    56         This library is dedicated to help the end-user to partition an applicattion for
    57         HPC.
     56        This library is dedicated to help the end-user to partition an application for HPC.
    5857      \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2.5:0}
    5958        \setMacroInAuxFile{hpcCommLinux}
    60         The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
    61         library and probably a LINUX module.
    62       \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
    63         \setMacroInAuxFile{hpcMutekDriver}
    64         The FPGA-SoC part of the communication API, a driver.
     59        The PC part of the HPC communication API that communicates with the FPGA-SOC, a
     60        library and a LINUX module.
     61%      \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:2.5:0}
     62%        \setMacroInAuxFile{hpcMutekDriver}
     63%        The FPGA-SoC part of the communication API, a driver.
    6564      \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
    6665        \setMacroInAuxFile{hpcDnaDriver}
    67         Port of the {\hpcMutekDriver} driver on the DNA OS.
    68       \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
    69         Bug corrections and enhancements of communication middleware
    70         (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
    71         \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
     66        The FPGA-SoC part of the communication API.
     67%        Port of the {\hpcMutekDriver} driver on the DNA OS.
     68%      \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
     69%        Bug corrections and enhancements of communication middleware
     70%        (\novers{\hpcCommApi}, \novers{\hpcCommHelper}, \novers{\hpcCommLinux},
     71%        \novers{\hpcMutekDriver}, \novers{\hpcDnaDriver}).
    7272    \end{livrable}
    7373
    74 \subtask This \ST deals with the implementation of hardware and SystemC modules
     74\subtask{SystemC model of the PCI/X}
     75    This \ST deals with the implementation of hardware and SystemC modules
    7576    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
    7677    \begin{livrable}
    77     \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
    78         \setMacroInAuxFile{hpcPlbBridge}
    79         The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
    80     \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
    81         \setMacroInAuxFile{hpcAvalonBridge}
    82         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
     78% FIXME: moved to task 3 (CSG)
     79%    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
     80%        \setMacroInAuxFile{hpcPlbBridge}
     81%        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
     82%    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
     83%        \setMacroInAuxFile{hpcAvalonBridge}
     84%        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
    8385    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
    8486        The SystemC description of a component that generates PCI/X traffic. It is
    … …  
    8688    \end{livrable}
    8789
    88 \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
    89 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
    90     \begin{livrable}
    91     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
    92         Modification of the CSG software to support statically reconfigurable tasks.
    93     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
    94                 This livrable is a CSG module allowing to partition the task graph along
    95                 the dynamic partial reconfiguration regions. The resulting task-region assignement
    96                 is directly used for generation of bitstreams. The module also produces reconfiguration
    97                 management software to be run on the SoC-FPGA.
    98     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
    99         \setMacroInAuxFile{hpcDynconfDriver}
    100             The drivers required by the DNA OS in order to manage dynamic partial
    101         reconfiguration inside the SoC-FPGA.
    102     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
    103         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
    104     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
    105         Extension of the HPC partionning helper in order to integrate dynamic partial
    106         reconfiguration dedicated features (reconfiguration time of regions, variable
    107         number of coprocessors).
    108     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
    109         \xilinx will work with \tima in order to better take into account during
    110         partitioning decisions specific constraints due to partial reconfiguration process.
    111         The deliverable is a document describing the \xilinx specific constraints.
    112     \end{livrable}
    113 %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    114 %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
    115 %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    116 %   \begin{livrable}
    117 %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
    118 %   \end{livrable}
     90% \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
     91% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
     92%     \begin{livrable}
     93%     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
     94%         Modification of the CSG software to support statically reconfigurable tasks.
     95%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
     96%               This livrable is a CSG module allowing to partition the task graph along
     97%               the dynamic partial reconfiguration regions. The resulting task-region assignement
     98%               is directly used for generation of bitstreams. The module also produces reconfiguration
     99%               management software to be run on the SoC-FPGA.
     100%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
     101%         \setMacroInAuxFile{hpcDynconfDriver}
     102%           The drivers required by the DNA OS in order to manage dynamic partial
     103%         reconfiguration inside the SoC-FPGA.
     104%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
     105%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
     106%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
     107%         Extension of the HPC partionning helper in order to integrate dynamic partial
     108%         reconfiguration dedicated features (reconfiguration time of regions, variable
     109%         number of coprocessors).
     110%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
     111%         \xilinx will work with \tima in order to better take into account during
     112%         partitioning decisions specific constraints due to partial reconfiguration process.
     113%         The deliverable is a document describing the \xilinx specific constraints.
     114%     \end{livrable}
     115% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     116% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
     117% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
     118% %   \begin{livrable}
     119% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
     120% %   \end{livrable}
    119121\end{workpackage}
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