Changeset 297 for anr/section-1.tex

Timestamp:

Dec 16, 2010, 2:13:23 PM (14 years ago)

Author:

coach

Message:

 

File:

• anr/section-1.tex (modified) (9 diffs)

anr/section-1.tex

@@ -27 +27 @@
 will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
 devices and to enter new, low and medium volume markets.
-\begin{ADDEDENV}
 Furthermore, today there is an increasing industrial interest to IC
 that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
@@ -34 +33 @@
 general purpose CPU cores will contains a configurable area making explode the low and medium volume
 markets of digital systems.
-\end{ADDEDENV}
 \parlf
-\begin{SUPPRESSEDENV}
-The objective of COACH is to provide an integrated design flow, based on the
-SoCLib infrastructure~\cite{soclib}, and optimized for the design of
-multi-processors digital systems targeting FPGA devices.
-The digital systems are generally integrated into one or several chips, and there are two types of applications:
-They can be embedded (autonomous) applications
-such as personal digital assistants (PDA), ambient computing components,
-or wireless sensor networks (WSN).
-They can also be extension boards connected to a PC to accelerate a specific computation,
-as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
-\end{SUPPRESSEDENV}\begin{ADDEDENV}
 The objective of COACH is to provide an integrated design flow for the design of
 multi-processors digital systems targeting FPGA devices.
@@ -57 +44 @@
    it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
 3) sub-system application for generating an IP to a larger system.
-\end{ADDEDENV}
 \parlf
 %verrous scientifiques et techniques
@@ -70 +56 @@
     For each point in the design space, metrics such as throughput, latency, power
     consumption, silicon area, memory allocation and data locality will be provided.
-    \begin{SUPPRESSEDENV}
-    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
-    and high-level estimation methodologies.
-    \end{SUPPRESSEDENV}
 \item[Hardware Accelerators Synthesis (HAS):]
     COACH will allow the automatic generation of hardware accelerators when required.
@@ -106 +88 @@
     communications between software tasks running on embedded processors and 
     dedicated hardware coprocessors.
-\begin{ADDEDENV}
-\item[Interaction with the industrial world]
+\item[Interaction with the industrial world:]
     COACH will not be a closed framework but it will be opened to the industrial
     world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
@@ -113 +94 @@
     This should facilitate the enhancement of the architectural template with IP and the
     integration of the IP produced by COACH in larger design.
-\end{ADDEDENV}
 \end{description}
-\begin{SUPPRESSEDENV}
-MOVED ABOVE
-The COACH design flow will be dedicated to system designers, and will as
-much as possible hide the hardware characteristics to the end-user.
-\end{SUPPRESSEDENV}
 %From the end user point of view, the specification of the application will be
 %independant from both the architectural template and from the selected FPGA
@@ -135 +110 @@
 ASIP architectures (\irisa),
 High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
-HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}.
+HPC (\bull, \thales), tools integration in IP-XACT flow (\mds).
 \\
 The COACH project does not start from scratch.
-\begin{SUPPRESSEDENV}
-It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
-(DSX, component library), operating systems (MUTEKH, DNA/OS).
-It also leverages on  several existing technologies:
-on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
-on the ROMA~\cite{roma} project for ASIP,
-on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
-and on the \xilinx and \altera IP core libraries.
-\end{SUPPRESSEDENV}\begin{ADDEDENV}
 It relies
+on the Magillem industrial platform for the integration into IP-XACT flows,
 on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
@@ -153 +120 @@
 on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
 transformations,
-on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem},
 and on the \xilinx and \altera IP core libraries.
-\end{ADDEDENV}
 Finally it will use the \xilinx and \altera logic and physical synthesis tools
 to generate the FPGA configuration bitstreams.
-\parlf
-The COACH proposal has been prepared during one year by a technical working group
-involving the 5 academic partners (one monthly meeting from january 2009 to february
-2010). The objective was to analyse the issues of integrating
-and enhancing the existing tools and technologies into a unique framework.
-Most of the general software architecture of the proposed design flow (including the
-exchange format specification) has been define by this working group.
-\SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be
-described as an extension of the SoCLib platform.}
 %The main development steps of the COACH project are: 
 %\begin{enumerate}
@@ -187 +143 @@
 %\end{enumerate}
 \parlf
-Two major FPGA companies are involved in the project: \xilinx will contribute
-as a contractual partner providing documentation and manpower; \altera will contribute as
-a supporter (see letter page \pageref{supp:1})
-providing documentation and development boards. These two companies are strongly motivated
-to help the COACH project to generate efficient bitstreams for both FPGA families.
 The role of the industrial partners \bull, \thales and \mds is to provide
 real use cases to benchmark the COACH design environment and to analyze the designer productivity 
 improvements. 
 \parlf
-\begin{SUPPRESSEDENV}
-Following the general policy of the SoCLib platform, the COACH project will be an open
-infrastructure, available in the framework of the SoCLib server.
-The architectural templates, and the COACH software tools will be distributed under the
-GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
-IP core library) will be freely available for non commercial use.
-\end{SUPPRESSEDENV}\begin{ADDEDENV}
-The COACH project will be an open infrastructure and freely distributed.
-The architectural templates and the COACH software tools will be distributed under the
-GPL license. The VHDL synthesizable models for the neutral architectural template
+The COACH project will deliver an open and freely distributed infrastructure.
+The architectural templates and most of the software tools will be distributed under the
+GPL-like license.
+The VHDL synthesizable models for the neutral architectural template
 will also be freely available for non commercial use.
-\end{ADDEDENV}
 For industrial exploitation the technology providers are ready to propose commercial licenses,
 directly to the end user, or through a third party.
 \parlf
 \mustbecompleted{LIST NON A JOUR}
+The major FPGA companies (\xilinx and \altera) have expressed their interest for
+this project.
 Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the 
 "letters of interest" (see Annex B), that have collected during the preparation of the project :