Changeset 297


Ignore:
Timestamp:
Dec 16, 2010, 2:13:23 PM (14 years ago)
Author:
coach
Message:
 
Location:
anr
Files:
6 edited

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  • anr/anr.tex

    r296 r297  
    5555\definecolor{rouge}{rgb}{1.0,0.2,0.2}
    5656\def\mustbecompleted#1{}
    57 \def\parlf{\noexpand\par\vspace*{1.0ex}}
     57\def\parlf{\mbox{}\vspace*{1.0ex}\\}
    5858\def\ADDED#1{\textcolor{blue}{#1}}
    5959\newenvironment{ADDEDENV}{\color{blue}}{}
    … …  
    119119\begin{minipage}{\linewidth}Theme\\\end{minipage}
    120120       & \setlength{\unitlength}{5.0mm}\begin{picture}(20,2)
    121         \put( 0.5,1.1){\boitecochee}                  \put( 1.5,0.9){1}
    122         \put( 3.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put( 4.5,0.9){2}
    123         \put( 6.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put( 7.5,0.9){3}
     121        \put( 0.5,0.9){\framebox(0.6,0.6){ }}         \put( 1.5,0.9){1}
     122        \put( 3.5,1.1){\boitecochee}                  \put( 4.5,0.9){2}
     123        \put( 6.5,0.9){\framebox(0.6,0.6){}}          \put( 7.5,0.9){3}
    124124        \put( 9.5,0.9){\framebox(0.6,0.6){ }}         \put(10.5,0.9){4}
    125125        \put(12.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put(13.5,0.9){5}
    … …  
    141141    \vspace*{0.5ex}Total requested \\ funding
    142142  \end{minipage}
    143     & \makebox[3cm]{1195931 \euro}
     143    & \makebox[3cm]{ \mustbecompleted{???} \euro}
    144144      & \begin{minipage}{4.15cm}\center Project Duration \end{minipage}
    145145        & \begin{minipage}{3cm}\center 36 months \end{minipage} \\\hline

  • anr/section-1.tex

    r290 r297  
    2727will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative
    2828devices and to enter new, low and medium volume markets.
    29 \begin{ADDEDENV}
    3029Furthermore, today there is an increasing industrial interest to IC
    3130that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA)
    … …  
    3433general purpose CPU cores will contains a configurable area making explode the low and medium volume
    3534markets of digital systems.
    36 \end{ADDEDENV}
    3735\parlf
    38 \begin{SUPPRESSEDENV}
    39 The objective of COACH is to provide an integrated design flow, based on the
    40 SoCLib infrastructure~\cite{soclib}, and optimized for the design of
    41 multi-processors digital systems targeting FPGA devices.
    42 The digital systems are generally integrated into one or several chips, and there are two types of applications:
    43 They can be embedded (autonomous) applications
    44 such as personal digital assistants (PDA), ambient computing components,
    45 or wireless sensor networks (WSN).
    46 They can also be extension boards connected to a PC to accelerate a specific computation,
    47 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
    48 \end{SUPPRESSEDENV}\begin{ADDEDENV}
    4936The objective of COACH is to provide an integrated design flow for the design of
    5037multi-processors digital systems targeting FPGA devices.
    … …  
    5744   it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP);
    58453) sub-system application for generating an IP to a larger system.
    59 \end{ADDEDENV}
    6046\parlf
    6147%verrous scientifiques et techniques
    … …  
    7056    For each point in the design space, metrics such as throughput, latency, power
    7157    consumption, silicon area, memory allocation and data locality will be provided.
    72     \begin{SUPPRESSEDENV}
    73     These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
    74     and high-level estimation methodologies.
    75     \end{SUPPRESSEDENV}
    7658\item[Hardware Accelerators Synthesis (HAS):]
    7759    COACH will allow the automatic generation of hardware accelerators when required.
    … …  
    10688    communications between software tasks running on embedded processors and
    10789    dedicated hardware coprocessors.
    108 \begin{ADDEDENV}
    109 \item[Interaction with the industrial world]
     90\item[Interaction with the industrial world:]
    11091    COACH will not be a closed framework but it will be opened to the industrial
    11192    world by using the IP-XACT format \cite{IP-XACT-08} for describing the components of the
    … …  
    11394    This should facilitate the enhancement of the architectural template with IP and the
    11495    integration of the IP produced by COACH in larger design.
    115 \end{ADDEDENV}
    11696\end{description}
    117 \begin{SUPPRESSEDENV}
    118 MOVED ABOVE
    119 The COACH design flow will be dedicated to system designers, and will as
    120 much as possible hide the hardware characteristics to the end-user.
    121 \end{SUPPRESSEDENV}
    12297%From the end user point of view, the specification of the application will be
    12398%independant from both the architectural template and from the selected FPGA
    … …  
    135110ASIP architectures (\irisa),
    136111High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
    137 HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}.
     112HPC (\bull, \thales), tools integration in IP-XACT flow (\mds).
    138113\\
    139114The COACH project does not start from scratch.
    140 \begin{SUPPRESSEDENV}
    141 It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
    142 (DSX, component library), operating systems (MUTEKH, DNA/OS).
    143 It also leverages on  several existing technologies:
    144 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
    145 on the ROMA~\cite{roma} project for ASIP,
    146 on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
    147 and on the \xilinx and \altera IP core libraries.
    148 \end{SUPPRESSEDENV}\begin{ADDEDENV}
    149115It relies
     116on the Magillem industrial platform for the integration into IP-XACT flows,
    150117on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
    151118on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
    … …  
    153120on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
    154121transformations,
    155 on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem},
    156122and on the \xilinx and \altera IP core libraries.
    157 \end{ADDEDENV}
    158123Finally it will use the \xilinx and \altera logic and physical synthesis tools
    159124to generate the FPGA configuration bitstreams.
    160 \parlf
    161 The COACH proposal has been prepared during one year by a technical working group
    162 involving the 5 academic partners (one monthly meeting from january 2009 to february
    163 2010). The objective was to analyse the issues of integrating
    164 and enhancing the existing tools and technologies into a unique framework.
    165 Most of the general software architecture of the proposed design flow (including the
    166 exchange format specification) has been define by this working group.
    167 \SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be
    168 described as an extension of the SoCLib platform.}
    169125%The main development steps of the COACH project are:
    170126%\begin{enumerate}
    … …  
    187143%\end{enumerate}
    188144\parlf
    189 Two major FPGA companies are involved in the project: \xilinx will contribute
    190 as a contractual partner providing documentation and manpower; \altera will contribute as
    191 a supporter (see letter page \pageref{supp:1})
    192 providing documentation and development boards. These two companies are strongly motivated
    193 to help the COACH project to generate efficient bitstreams for both FPGA families.
    194145The role of the industrial partners \bull, \thales and \mds is to provide
    195146real use cases to benchmark the COACH design environment and to analyze the designer productivity
    196147improvements.
    197148\parlf
    198 \begin{SUPPRESSEDENV}
    199 Following the general policy of the SoCLib platform, the COACH project will be an open
    200 infrastructure, available in the framework of the SoCLib server.
    201 The architectural templates, and the COACH software tools will be distributed under the
    202 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
    203 IP core library) will be freely available for non commercial use.
    204 \end{SUPPRESSEDENV}\begin{ADDEDENV}
    205 The COACH project will be an open infrastructure and freely distributed.
    206 The architectural templates and the COACH software tools will be distributed under the
    207 GPL license. The VHDL synthesizable models for the neutral architectural template
     149The COACH project will deliver an open and freely distributed infrastructure.
     150The architectural templates and most of the software tools will be distributed under the
     151GPL-like license.
     152The VHDL synthesizable models for the neutral architectural template
    208153will also be freely available for non commercial use.
    209 \end{ADDEDENV}
    210154For industrial exploitation the technology providers are ready to propose commercial licenses,
    211155directly to the end user, or through a third party.
    212156\parlf
    213157\mustbecompleted{LIST NON A JOUR}
     158The major FPGA companies (\xilinx and \altera) have expressed their interest for
     159this project.
    214160Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the
    215161"letters of interest" (see Annex B), that have collected during the preparation of the project :

  • anr/section-2.tex

    r237 r297  
    88software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
    99Only very few SMEs have these multiple expertises and are present on the embedded system market.
     10Furthermore, even small design services in the big companies are facing the same issue.
    1011\begin{center}\begin{minipage}{.8\linewidth}\textit{
    11 The major objective of COACH is to provide to SMEs an open-source framework to design
    12 embedded systems on FPGA devices by system designers.
     12The major objective of COACH is to provide to system designers, an affordable
     13open-source framework to design embedded systems on FPGA devices.
    1314}\end{minipage}\end{center}
    1415%Current design methodologies provide quite low-level abstraction capabilities, and
    … …  
    1920%%%
    2021\parlf
    21 The COACH project will leverage on the expertise gained in the field of virtual prototyping
    22 with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
     22The COACH project will propose a new design flow based on a small number of architectural templates.
    2323An architectural template is a generic, parameterized architecture, relying on a predefined library
    2424of IP cores.
    … …  
    4242When this interactive, system level, design space exploration is completed (converging to
    4343a specific mapping on a specific version of the selected architectural template), the rest of the flow
    44 is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary
    45 code for the software running on the embedded processors, and the bit-stream to program the the target FPGA
     44is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
     45code for the software running on the embedded processors, and the bit-stream to program the target FPGA
    4646will be automatically generated by the COACH tools.
    4747%
    … …  
    5050in a platform based design flow supporting virtual prototyping and design space exploration.
    5151Most building blocks already exist (resulting from previous projects): the GAUT
    52 or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology,
    53 the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
    54 as well as the SoCLib library of systemC simulation models. They must now be enhanced and integrated in
    55 a consistent design flow.
     52or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
     53the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
     54as well as the SoCLib library of SystemC simulation models.
     55They must now be enhanced and integrated in a consistent design flow: this will
     56be done in Magillem framework thanks to the IP-XACT standard.
    5657%The five academic laboratories worked very closely during more than one year (one monthly meeting
    5758%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
    … …  
    5960%%%
    6061\parlf
    61 In HPC (High Performance Computing), the targeted application is an existing application
     62In HPC (High Performance Computing), the targeted application is an existing one
    6263running on a PC.
    6364The COACH framework helps designer to accelerate it by migrating critical parts into a
    6465SoC embedded into an FPGA device plugged to the PC PCI/X bus.
    6566\begin{center}\begin{minipage}{.8\linewidth}\textit{
    66 The second objective of COACH is to extend the framework to HPC.
     67The second objective of COACH is to extend the framework for HPC applications.
    6768}\end{minipage}\end{center}
    6869This will allow SMEs to enter HPC market for the applications that are
    6970unadapted to the current GPU based solutions.
    7071%%%
    71 \parlf
    72 In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
    73 have been previously developed by academic laboratories.
    74 
    75 
    76 %Finally, the key points of the proposed design flow are :
    77 %\begin{itemize}
    78 %\item
    79 %\textbf{System level exploration}: The application coarse grain parallelism
    80 %is explicitely described as a Tasks and Communication Graph (TCG).
    81 %A template architecture is selected, and the performances are evaluated
    82 %on various variant of this architecture using the SoCLib virtual protyping
    83 %environment. This result in a specific hardware/software partitioning. 
    84 %This system level exploration is fully controlled by the system designer, and is driven
    85 %by cost, throughput, latency and power consumption criteria.
    86 %
    87 %\item
    88 %\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
    89 %identified as mandatory, they will be generated by the high level synthesis (HLS) tools.
    90 %The COACH framework will integrate various HLS tools, supporting the micro-architectural space
    91 %design exploration. Here again, the exploration criteria are cost, throughput, latency
    92 %and power consumption.
    93 %At this stage, preliminary source-level transformations and optimisations by front-end
    94 %tools will be required to improve the efficiency of the back-end HLS tools.
    95 %
    96 %\item
    97 %\textbf{Early performance evaluation}: For each point in the design space,
    98 %figures of merit must be available such as throughput, latency, power
    99 %consumption, area, memory allocation and data locality. They are evaluated
    100 %by reliable estimators obtained by running the actual multi-task software
    101 %application on the virtual prototype.
    102 %
    103 %\item
    104 %\textbf{Independance from the Target FPGA}: The COACH description of the system
    105 %(both hardware and software) should be independent of the FPGA family. 
    106 %Every point of the design space can be implemented on any FPGA component,
    107 %as long as it contains the hardware ressources required by the selected architectural template.
    108 %Basically, COACH will support both \altera and \xilinx FPGA families.
    109 %\end{itemize}
    110 %
    111 
    112 
    113 

  • anr/section-objectif.tex

    r289 r297  
    1111% les objectifs scientifiques/techniques du projet.
    1212The design steps are presented figure~\ref{coach-flow}.
    13 \ADDED{
    1413The end-user input is
    15 either a HPC application (an application running on a PC that must be accelarate),
     14either a HPC application (an application running on a PC that must be accelerate),
    1615or an embedded application (a standalone application),
    1716or a  sub-system application of a larger design.
    … …  
    1918except in the generation step and that the design flow of HPC application just adds a
    2019preliminary step.
    21 }
    2220\begin{figure}[hbtp]\leavevmode\center
    2321  \includegraphics[width=1.0\linewidth]{flow2}
    … …  
    3836ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
    3937and hardware (the process is implemented as a synthesized hardware coprocessor).
    40 \begin{SUPPRESSEDENV}
    41 \item[Application compilation:]
    42 Once the SoC architecture is validated through performances analysis,
    43 COACH will generate automatically an executable containing the host application and
    44 the FPGA bitstream. This bitstream contains
    45 both the hardware architecture and the SoC application software.
    46 The user will be able to launch the application by
    47 loading the bitstream on an FPGA and running the executable on PC.
    48 \end{SUPPRESSEDENV}\begin{ADDEDENV}
    4938\item[Generation:]
    5039Once the SoC architecture is validated through performances analysis,
    … …  
    5544also generated and the user will be able to launch the application by loading
    5645the bitstream on an FPGA and running the executable on PC.
    57 \end{ADDEDENV}
    5846\end{description}
    5947 

  • anr/section-position.tex

    r289 r297  
    3737\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
    3838environment, suitable for co-operative and distributed development.
     39\item \mustbecompleted{IP-XACT: .... MAGILLEM...}
    3940\end{itemize}
    4041COACH outcome will contribute to strengthen Europe's competitive position by developing
    … …  
    5354\begin{description}
    5455  \item[SOCLIB]
    55     The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
    56     10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
    57     industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept).
    58     It supports system level virtual prototyping of shared memory, multi-processors
     56    The SoCLib ANR platform (2007-2009) is an open infrastructure
     57    that supports system level virtual prototyping of shared memory, multi-processors
    5958    architectures, and provides tools to map multi-tasks software application on these
    6059    architectures, for reliable performance evaluation.
    6160    The core of this platform is a library of SystemC simulation models for
    62     general purpose IP cores such as processors, buses, networks, memories, IO controller.
    63     The platform provides also embedded operating systems and software/hardware
     61    general purpose IP cores.
     62    It provides also embedded operating systems and software/hardware
    6463    communication middleware.
    65     The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    66     COACH will enhance SoCLib by providing the synthesisable VHDL models required
    67     for FPGA synthesis.
    6864  \item[ROMA] The ROMA ANR project \cite{roma}
    6965    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
    … …  
    9288    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    9389    be able to validate the framework on real-life HPC applications.
     90  \item[SoCket]  \mustbecompleted{...... MAGILEM ......}
     91  \item[HOSPI]   \mustbecompleted{...... MAGILEM ......}
     92  \item[SoftSoc] \mustbecompleted{...... MAGILEM ......}
    9493\end{description}
    9594%%%
    9695\parlf\noindent
    97 The laboratories involved in the COACH project have a well estabished expertise
    98 %in the following domains:
    99 in the domains:
     96The partners involved in the COACH project have a well established expertise
     97in the following domains:
    10098\begin{itemize}
    10199  \item
    102100    In the field of High Level Synthesis (HLS), the project
    103101    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
    104     developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
     102    developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed
    105103    by the \upmc and \tima laboratories.
    106104  \item
    … …  
    116114    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
    117115    compilers~\cite{ASAP05} since 2002).
    118 \item
     116  \item
    119117    In the field of compilers, the \lip Compsys group was founded in 2002
    120118    by several senior researchers with experience in
    … …  
    126124    process construction \cite{Feau:96} and memory management \cite{bee}
    127125    will be very useful as a front-end for HLS tools.
     126  \item
     127    Regarding \mustbecompleted{.... MAGILLEM ... IP-XACT}
    128128\end{itemize}
    129129%%%
    130130\parlf\noindent
    131 The COACH project answers to several of the challenges found in different axis of the
    132 call for proposals.%Keywords of the call are indicated below in italic writing.
    133 \begin{description}
    134 \item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\
     131The COACH project totally fulfills the objectives of the axis 2 "METHODES,
     132OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES".
     133\mustbecompleted{BEGIN-FIXME}
    135134COACH will address new embedded systems architectures by allowing the design of
    136135Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
    … …  
    140139API and using hardware accelerator automatically generated. It will also permit to use
    141140efficiently different dynamic system management techniques and re-configuration mechanisms.
    142 \textbf{Thereby COACH well corresponds to axis 1}.
    143 %
    144 \item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
     141\\
    145142COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
    146143application running on a PC.
    … …  
    148145configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the
    149146PC bus (through a communication link like PCI/X).
    150 Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance
    151 as well as reducing the required area.
    152 \textbf{Thereby COACH partially corresponds to axis 2}.
    153 %
    154 % IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et
    155 % IA2PC: secondaire.
    156 %VERS 3
    157 %\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\
    158 %Manufacturing technology employs more and more SoC.
    159 %COACH will permit to design such complex digital systems.
    160 %\textbf{Thereby COACH indirectly answers to axis 3 too}.
    161 
    162 
    163 %\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
    164 %VERS 1
    165 %Future control applications employ more and more SoC.
    166 %Application domains for such systems are for example the automotive domain, as well as the
    167 %aerospace and avionics domains.
    168 %In all cases, high performance and real time requirements are combined with
    169 %requirements to low power, low temperature, high dependability, and low cost.\\
    170 %Similary manufacturing, security and safety technologies require also more and more
    171 %computation power.
    172 %VERS 2 pour gagner de la place
    173 %Manufacturing, controling, security and safety technologies employ more and more SoC.
    174 %COACH will permit to design such complex digital systems.
    175 %\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
    176 
    177 %\end{description}
    178 
    179 \item [Axis 3] \textit {Robotique et contr\^{o}le/commande}:
    180 
     147\mustbecompleted{END-FIXME}
     148\parlf
     149The COACH project well fits also the axis 5 "USAGES".
     150\mustbecompleted{BEGIN-FIXME}
    181151COACH will address robotic and control applications by
    182152allowing to design complex systems based on MPSoC architecture.
    … …  
    187157Manufacturing technology will also increasingly need high-end vision analysis and high-speed
    188158robot control.
    189 \textbf{Thereby COACH indirectly answers to axis 3}.
    190 
    191 \item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}:
    192 
     159%
    193160The results of the COACH project will help users to build cryptographic secure systems implemented in
    194161hardware or both in software/hardware in an effective way, substantially enhancing the
    195162process productivity of the cryptographic algorithms hardware synthesis, improving the
    196163quality and reducing the design time and the cost of synthesised cryptographic devices.
    197 \textbf{Thereby COACH indirectly answers to axis 5}.
    198 
    199 \end{description}
    200 
    201 % IA2PC: 1) je ne vois pas trop ce que ca fait la.
    202 % IA2PC: 2) c'est deja dans le 2.1 pour le small business.
    203 % IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense
    204 % IA2PC     toujours que le large business est encore vise par COACH.
    205 % IA2PC     Alain a enleve toute reference sur ce large business. Sa raison est +
    206 % IA2PC     politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille
    207 % IA2PC     le message. Je partage assez son avis, la version actuelle est + claire que
    208 % IA2PC     celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses
    209 % IA2PC     boites.
    210 % IA2PC
    211 % IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large
    212 % IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans
    213 % IA2PC les sections precedentes.
    214 %
    215 % VERS 2 pour gagner de la place je l'enleve
    216 
    217 %PC2IA ok pas de probleme
    218 
    219 % COACH technologies can be used in both large and small business, as they will permit users to design
    220 % embedded systems which meet a wide range of requirements: from low cost and low power consuming
    221 % devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
    222 % systems designed via the approaches and tools targeted by COACH, there is the potential for greater
    223 % efficiency, improved business processes and models. The net results: lower costs, faster response times,
    224 % better service, and higher revenue.
    225 %\parlf
     164\mustbecompleted{END-FIXME}
     165\parlf
    226166Finally, it is worth to note that this project covers priorities defined by the commission
    227167experts in the field of Information Technolgies Society (IST) for Embedded

  • anr/section-project-description.tex

    r289 r297  
    4040controls the HAS tools described below.
    4141From these inputs \verb!CSG! can generate the entire system (both software and
    42 hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger
    43 design or}
     42hardware) either as an IP under IP-XACT to integrate the SoC in larger
     43design or
    4444as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the
    4545design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
    … …  
    4747FPGA device\footnote{Additional partial bitstreams are generated in case of
    4848 dynamic partial reconfiguration}.
    49  \begin{ADDEDENV}
    5049 \\
    5150 Furthermore the architecture template and hardware component libraries will be described
    52  under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other
     51 under the IP-XACT specification to facilitate the configuration of \verb+CSG+ to other
    5352 architecture or the enhancement of existing template with IP.
    54  \end{ADDEDENV}%
    5553\parlf
    5654The software architecture for HAS is presented in figure~\ref{archi-hls}.
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