Changeset 297 for anr/section-project-description.tex

Timestamp:

Dec 16, 2010, 2:13:23 PM (14 years ago)

Author:

coach

Message:

 

File:

• anr/section-project-description.tex (modified) (2 diffs)

anr/section-project-description.tex

@@ -40 +40 @@
 controls the HAS tools described below.
 From these inputs \verb!CSG! can generate the entire system (both software and
-hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger
-design or}
+hardware) either as an IP under IP-XACT to integrate the SoC in larger
+design or
 as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
@@ -47 +47 @@
 FPGA device\footnote{Additional partial bitstreams are generated in case of
  dynamic partial reconfiguration}.
- \begin{ADDEDENV}
  \\
  Furthermore the architecture template and hardware component libraries will be described
- under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other
+ under the IP-XACT specification to facilitate the configuration of \verb+CSG+ to other
  architecture or the enhancement of existing template with IP.
- \end{ADDEDENV}%
 \parlf
 The software architecture for HAS is presented in figure~\ref{archi-hls}.