Changeset 3 for anr


Ignore:
Timestamp:
Nov 26, 2009, 10:47:11 AM (15 years ago)
Author:
coach
Message:

Minor changes

Location:
anr
Files:
2 edited

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  • anr/anr.tex

    r1 r3  
    1010\usepackage{xmpmulti}
    1111\usepackage{graphicx}
     12\usepackage{color}
     13
     14\definecolor{gris25}{gray}{0.75}
     15\definecolor{gris75}{gray}{0.30}
    1216
    1317\title{%
    1418\textbf{COACH:}
    1519\textbf{C}onception d'\textbf{A}rchitecture par
    16 \textbf{C}ompilation et synt\textbf{H}èse
     20\textbf{C}ompilation et synt\textbf{H}ï¿œse
    1721}
    1822

  • anr/body.tex

    r2 r3  
    1919due to the design and fabrication costs.
    2020Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx and Stratix4 from Altera,
    21 can implement a SoC with multiple processors and several coprocessors for less than 10K euros the piece.
    22 In addition, High Level Synthesis (HLS) becomes more mature and allows to automize design
    23 and to decrease drastically its cost in terms of man power. Thus, both FPGA and HLS tends to spread over
    24 HPC for small companies targeting low volume markets.
     21can implement a SoC with multiple processors and several coprocessors for less than 10K euros
     22per item. In addition, High Level Synthesis (HLS) becomes more mature and allows to automate
     23design and to drastically decrease its cost in terms of man power. Thus, both FPGA and HLS
     24tend to spread over HPC for small companies targeting low volume markets.
    2525\par
    2626To get an efficient embedded system, designer has to take into account application characteristics when it
    … …  
    111111various application domains. The ``high end'' lines concern only FPGA with high logic capacity able
    112112to implement complex systems.
    113 This market is in significant expansion and is estimated to 914 M\$ in 2012.
     113This market is in significant expansion and is estimated to 914\,M\$ in 2012.
    114114Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies
    115115and tools to automize design and reduce its cost.
    … …  
    140140segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
    141141emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers
    142 to 214 M\$.
     142to 214\,M\$.
    143143This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
    144144of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial
    … …  
    149149a synthesized netlist, simulation test bench and custom software library that reflect the hardware
    150150configuration.
    151 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
     151Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
     152(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
    152153simulate the platform at a high design level (system C).
    153154In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
    … …  
    163164However, this tool targets only DSP based algorithms.
    164165\\
    165 Consequently, designer developping an embedded system needs to master for example
     166Consequently, designers developping an embedded system needs to master for example
    166167SoCLib for design exploration,
    167168SOPC Builde at the platform level,
    … …  
    169170and Quartus for design implementation.
    170171This requires an important tools interfacing effort and makes the design process very complex
    171 and achievable only by designers skilled in various domains.
     172and achievable only by designers skilled in many domains.
    172173COACH project integrates all these tools in the same framework masking them to the user.
    173174The objective is to allow \textbf{pure software} developpers to realize embedded systems.
    … …  
    206207extraction algorithms and datapath merging techniques to the synthesis of customized
    207208ASIP processors.
     209\\
     210\textcolor{gris75}{Steven : Je propose de rajouter un lien avec le projet BioWic~:~on the HPC
     211application side, we also hope to benefit from the experience in hardware acceleration of
     212bioinformatic algorithms/workfows gathered by the CAIRN group in the context of the ANR
     213BioWic project (2009-2011), so as to be able to validate the framework on
     214real-life HPC applications.}
     215
    208216\par
    209217%%% 1 -- POUVEZ VOUS CHACUN AJOUTER SVP (SI POSSIBLE) UNE LIGNE
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