Changeset 304


Ignore:
Timestamp:
Dec 23, 2010, 11:53:37 AM (14 years ago)
Author:
coach
Message:

MAJ des donnees LIP6 (quasi la derniere)

Location:
anr
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • anr/annexe-autre-participation.tex

    r303 r304  
    2121\autreprojettabularentry
    2222    {5}{Greiner}{13}
    23     {\mustbecompleted{FIXME-exemple}Tsar, UE, 200 k\euro}
    24     {\mustbecompleted{Term Smart Argh Real}}
    25     {Dupont}
    26     {01/01/2008 12/31/2010}
     23    {Tsar, CATRENE, 500 k\euro}
     24    {Tera Scale ARchitecture}
     25    {Nam Nguyen (Bull)}
     26    {01/01/2008 05/31/2011}
    2727
    2828\end{autreprojettabular}

  • anr/annexe-cv.tex

    r303 r304  
    1919
    2020\begin{cvenv}
     21  {{Greiner}{Alain}{58}}
     22  {Professeur UMPC}
     23  {HDR Thesis (1982)}
     24  {{100}{\cite{ag-1} \cite{ag-2} \cite{ag-3} \cite{ag-4}}}
     25 
     26  \item[Projects]\mbox{}
     27    \begin{itemize}
     28      \item Work on TSAR CATRENE project \cite{disydent05}.
     29      \item Worked on SoCLib ANR project\cite{disydent05}.
     30      \item Worked on COSY european project \cite{cosy}.
     31    \end{itemize}
     32\end{cvenv}
     33%
     34\begin{cvenv}
    2135  {{Aug\'e}{Ivan}{50}}
    2236  {Ma\^itre de conf\'erences at ENSIIE (Evry Essonne)}

  • anr/anr.bib

    r303 r304  
    761761}
    762762
     763%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     764%%% AG
     765
     766@article{ag-1,
     767    author = {Zhen Zhang and Alain Greiner and Mounir Benabdenbi},
     768    title = {Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components},
     769    journal ={On-Line Testing Symposium, IEEE International},
     770    volume = {0},
     771    isbn = {978-1-4244-7724-1},
     772    year = {2010},
     773    pages = {194-196},
     774    doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2010.5560209},
     775    publisher = {IEEE Computer Society},
     776    address = {Los Alamitos, CA, USA},
     777}
     778
     779@inproceedings{ag-2,
     780    author    = {Greiner Alain and Faure Etienne and Pouillon Nicolas and Genius Dani\'ela},
     781    title     = {A Generic Hardware/Software Communication Middleware for
     782                 Streaming Applications on Shared Memory Multi Processor Systems-on-Chip},
     783    booktitle = {Forum on Specification \& Design Languages (FDL 2009)},
     784    isbn      = { 978-2-9530504-1-7},
     785    month     = {September},
     786    year      = {2009},
     787    address   = {Nice, France},
     788}
     789
     790@inproceedings{ag-3,
     791    author    = {Porquet, Jo\"{e}l and Schwarz, Christian and Greiner, Alain},
     792    title     = {Multi-compartment: A new architecture for secure
     793                 co-hosting on SoC },
     794    booktitle = {Proceedings of the 11th international conference on System-on-chip},
     795    series    = {SOC'09},
     796    month     = {October},
     797    year      = {2009},
     798    isbn      = {978-1-4244-4466-3},
     799    location  = {Tampere, Finland},
     800    pages     = {124-127},
     801    numpages  = {4},
     802    url       = {http://portal.acm.org/citation.cfm?id=1736530.1736555},
     803    publisher = {IEEE Press},
     804    address   = {Piscataway, NJ, USA},
     805}
     806
     807@inproceedings{ag-4,
     808    author    = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain},
     809    title     = {Physical Implementation of the DSPIN Network-on-Chip in the
     810                 FAUST Architecture},
     811    booktitle = {Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip},
     812    series    = {NOCS'08},
     813    year      = {2008},
     814    month     = {April},
     815    isbn      = {978-0-7695-3098-7},
     816    location  = {Newcastle, UK},
     817    pages     = {139-148},
     818    numpages = {10},
     819    url = {http://portal.acm.org/citation.cfm?id=1397757.1397994},
     820    publisher = {IEEE Computer Society},
     821    address   = {Washington, DC, USA},
     822}
     823
     824
     825
     826%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     827%%% XXXX
     828

  • anr/anr.sty

    r300 r304  
    1 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    2 \catcode`\@=11
    3 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    4 
    51%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    62\newlength{\desclen}
    … …  
    84\newlength{\mmlen}
    95
    10 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    11 %{\catcode`\<=1\catcode`\>=2
    12 %       <\catcode`\{=12\gdef\OBraceTw<{>>
    13 %       <\catcode`\}=12\gdef\CBraceTw<}>>
    14 %>
    15 %\@ifundefined{specHasManual}{\let\specHasManual\relax}{}
     6\newbox\livrable@box
     7\newbox\tmp@box
     8
    169\let\specHasManual\relax
    1710\let\specCsgManual\relax
    18 \let\specXilinxOptimization\relax
    19 
     11
     12%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    2013\def\eoa{end-of-args}
    2114\def\@@novers#1-#2\eoa{#1}
    2215\def\@novers#1{\ifx\relax#1\def\next{{\color{red}FIXME}}\else\def\next{\expandafter\@@novers#1\eoa}\fi\next}
    2316
    24 \def\setMacroInAuxFile#1{%
    25         \hypertarget{#1}{}\vspace{-1.5ex}%
    26         \let\@novers\relax%
    27     \global\expandafter\edef\csname NOLNK#1\endcsname{\name}%
    28     \global\expandafter\edef\csname #1\endcsname{\noexpand\hyperlink{#1}{\name}}%
    29     \global\expandafter\edef\csname NOVERS#1\endcsname{\noexpand\hyperlink{#1}{\@novers{\name}}}%
    30     \global\expandafter\edef\csname NOVL#1\endcsname{\@novers{\name}}%
    31     \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOLNK#1\endcsname{\name}}%
    32     \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname #1\endcsname{\string\hyperlink{#1}{\name}}}%
    33     \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVERS#1\endcsname{\string\hyperlink{#1}{\@novers{\name}}}}%
    34     \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVL#1\endcsname{\@novers{\name}}}%
    35 }
     17\def\@hypertarget@cor{0pt}
     18\def\setMacroInAuxFile#1#2{%
     19%\mbox{}{\hypertarget{#1}{}\vspace{-1.0ex}}%
     20\hypertarget{#1}{}\gdef\@hypertarget@cor{1.5ex}%
     21\let\@novers\relax%
     22\global\expandafter\edef\csname NOLNK#1\endcsname{\name}%
     23\global\expandafter\edef\csname #1\endcsname{\noexpand\hyperlink{#1}{\name}}%
     24\global\expandafter\edef\csname NOVERS#1\endcsname{\noexpand\hyperlink{#1}{\@novers{\name}}}%
     25\global\expandafter\edef\csname NOVL#1\endcsname{\@novers{\name}}%
     26\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOLNK#1\endcsname{\name}}%
     27\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname #1\endcsname{\string\hyperlink{#1}{\name}}}%
     28\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVERS#1\endcsname{\string\hyperlink{#1}{\@novers{\name}}}}%
     29\immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVL#1\endcsname{\@novers{\name}}}%
     30#2}
    3631
    3732%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    8277\newwrite\ganttdata
    8378\immediate\openout\ganttdata=anr.gantt
     79\def\write@ganttdata#1{{
     80    \let\xcoach\relax%
     81    \let\xcoachplus\relax%
     82    \let\irisa\relax    \let\Sirisa\relax%
     83    \let\lip\relax      \let\Slip\relax%
     84    \let\tima\relax     \let\Stima\relax%
     85    \let\ubs\relax      \let\Subs\relax%
     86    \let\upmc\relax     \let\Supmc\relax%
     87    \let\altera\relax   \let\Saltera\relax%
     88    \let\bull\relax     \let\Sbull\relax%
     89    \let\thales\relax   \let\Sthales\relax%
     90    \let\mds\relax      \let\Smds\relax%
     91    \let\xilinx\relax%
     92    \immediate\write\ganttdata{#1}
     93}}
    8494
    8595\def\enable{enable}
    … …  
    133143\newcount\subtaskcnt
    134144\newcount\livrablecnt
    135 \newenvironment{workpackage}%
    136 {\global\advance\taskcnt1
    137  \global\subtaskcnt0
    138  \def\taskname{T\the\taskcnt}%
    139  \begin{description}%
    140  %\let\itemsave\item%
    141  \def\subtask##1{%
     145
     146 \def\@subtask#1{%
    142147    \global\advance\subtaskcnt1
    143148    \def\subtaskname{S\taskname-\the\subtaskcnt}%
    144     \item[\subtaskname: ##1]%
     149    \write@ganttdata{STN=\the\taskcnt\space\the\subtaskcnt\space#1}%
     150    \item[\subtaskname: #1]%
    145151    \IfFileExists{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex}%
    146152      {(\input{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex})}%
    147153      {\message{SKIPPING tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex files}}%
    148   \mbox{}\\%
    149   {%
    150     \let\xcoach\relax%
    151     \let\xcoachplus\relax%
    152     \let\irisa\relax    \let\Sirisa\relax%
    153     \let\lip\relax      \let\Slip\relax%
    154     \let\tima\relax     \let\Stima\relax%
    155     \let\ubs\relax      \let\Subs\relax%
    156     \let\upmc\relax     \let\Supmc\relax%
    157     \let\altera\relax   \let\Saltera\relax%
    158     \let\bull\relax     \let\Sbull\relax%
    159     \let\thales\relax   \let\Sthales\relax%
    160     \let\mds\relax      \let\Smds\relax%
    161     \let\xilinx\relax%
    162     \immediate\write\ganttdata{%
    163         STN=\the\taskcnt\space\the\subtaskcnt\space##1
    164     }%
    165  }}%
    166 }{%
    167   \end{description}}
    168 
    169 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    170 \def\writeganttinfo#1#2#3#4#5#6{{%
    171     \let\xcoach\relax
    172     \let\xcoachplus\relax
    173     \let\irisa\relax    \let\Sirisa\relax
    174     \let\lip\relax      \let\Slip\relax
    175     \let\tima\relax     \let\Stima\relax
    176     \let\ubs\relax      \let\Subs\relax
    177     \let\upmc\relax     \let\Supmc\relax
    178     \let\altera\relax   \let\Saltera\relax
    179     \let\bull\relax     \let\Sbull\relax
    180     \let\thales\relax   \let\Sthales\relax
    181     \let\mds\relax      \let\Smds\relax
    182     \let\xilinx\relax
    183     \immediate\write\ganttdata{%
     154    \mbox{}\\%
     155}
     156
     157\newenvironment{workpackage}{%
     158    \global\advance\taskcnt1%
     159    \global\subtaskcnt0%
     160    \def\taskname{T\the\taskcnt}%
     161    \begin{description}%
     162    \let\subtask\@subtask%
     163}{ \end{description}}
     164
     165%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     166\def\writeganttinfo#1#2#3#4#5#6{%
     167    \write@ganttdata{%
    184168      L=1 T=\the\taskcnt\space S=\the\subtaskcnt\space%
    185169      D=\the\livrablecnt\space V=\vers\space%
    186170      BM=#1 EM=#2 R=#3 PART={#4} KIND={#5} TITLE=#6%
    187     }
    188 }}
    189 \newenvironment{livrable}%
    190 {%
    191  \newcount\verscnt\verscnt=-1
    192  \newif\ifIsLivrableStarted\IsLivrableStartedfalse
    193  \newif\ifLivrableTopLine\LivrableTopLinetrue
    194  \def\livrableTableDef{\begin{tabular}{|c|c|c|c|p{.625\linewidth}|}\hline}
    195  \def\livrableTableLine##1##2##3##4{%
    196     \makebox[3.5em]{\begin{small}##1\end{small}} &
    197     \makebox[2.2em]{\begin{small}##2\end{small}} &
    198     \makebox[1.5em]{\begin{small}##3\end{small}} &
    199     \makebox[2.2em]{\begin{small}##4\end{small}} &
    200  }
    201  \def\livrableTableTopLine{%
    202    \livrableTableLine{number}{date}{type}{resp.} description
    203  }
    204  \livrablecnt-1
     171    }%
     172}
     173
     174\def\livrable@description@width{13.5cm}
     175\def\livrable@description@width{10.4cm}
     176\newif\if@livrable@firsttable@
     177\newif\if@livrable@table@MustBeOpened@
     178\newif\if@livrable@table@MustBeClosed@
     179\newif\if@livrable@table@MustBeClosed@after@
     180\let\librable@table@print@addon\relax
     181\def\livrable@table@begin{\begin{tabular}{|p{3.5em}|c|c|c|l|}\hline}
     182\def\livrable@table@line#1#2#3#4#5#6{
     183    \makebox[3.5em][c]{\begin{small}#1\end{small}} &
     184    \makebox[2.2em]{\begin{small}#2\end{small}} &
     185    \makebox[1.5em]{\begin{small}#3\end{small}} &
     186    \makebox[2.2em]{\begin{small}#4\end{small}} &
     187    #5\\#6}
     188\def\livrable@table@end{\end{tabular}\\}
     189\def\livrable@print@table{%
     190    \if@livrable@table@MustBeOpened@%
     191        \livrable@table@begin%
     192        \global\@livrable@table@MustBeOpened@false%
     193    \fi%
     194    \if@livrable@firsttable@%
     195        \livrable@table@line{number}{date}{type}{resp.}{description}{\hline\hline}%
     196    \fi%
     197    \global\@livrable@firsttable@false%
     198    \livrable@table@line%
     199        {\textsc{\name}}%
     200        {\textsc{T0+\livrableEndDate}}%
     201        {\textsc{\livrableType}}%
     202        {\textsc{\livrableLeader}}%
     203        %{\mbox{\copy\livrable@box}}{\hline}%
     204        %{\raisebox{\@hypertarget@cor}[\ht\livrable@box][\ht\livrable@box]{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}%
     205        {\raisebox{\@hypertarget@cor}{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}%
     206%        {}{\cline{2-5}}%
     207%    %& \multicolumn{4}{l|}{\raisebox{\@hypertarget@cor}{\copy\livrable@box}}\\\hline%
     208%    & \multicolumn{4}{l|}{{\copy\livrable@box}}\\\hline%
     209    \if@livrable@table@MustBeClosed@%
     210        \livrable@table@end%
     211        \global\@livrable@table@MustBeOpened@true%
     212        \global\@livrable@table@MustBeClosed@false%
     213    \fi%
     214    \if@livrable@table@MustBeClosed@after@%
     215        \global\@livrable@table@MustBeClosed@true%
     216        \global\@livrable@table@MustBeClosed@after@false%
     217    \fi%
     218    \global\def\@hypertarget@cor{0pt}%
     219    \global\let\librable@table@print@addon\relax%
     220}
     221
     222\def\@livrable@desc@box@start{%
     223  \begin{lrbox}{\livrable@box}\begin{minipage}[t]{\livrable@description@width}%
     224  \fontsize{11.0pt}{10pt}\selectfont%
     225  \let\ia@description\description%
     226  \def\description{\vspace*{-1.5ex}\ia@description\itemsep=1pt\topsep2pt\parskip0pt}%
     227  %\let\ia@enddescription\enddescription%
     228  %\newenvironment{description}{%
     229  %}{\ia@enddescription}%
     230}
     231
     232\def\@livrable@desc@box@start@eatCR#1{\@livrable@desc@box@start#1}
     233%\def\tmp{
     234%}
     235%\def\eat{\message{AAAAAAAAAAAAA:EAT}\@livrable@desc@box@start}
     236%\if\noexpand\nexttok\tmp
     237%    \message{AAAAAAAAAAAAAAAAAAAAA:OUI}%
     238%    \def\cont{\eat}%
     239%\else%
     240%    \message{AAAAAAAAAAAAAAAAAAAAA:NON}%
     241%    \def\cont{\@livrable@desc@box@start}%
     242%\fi%
     243%\cont}
     244
     245
     246\def\@itemV@next#1#2#3#4#5{\livrable@print@table\@itemV@first{#1}{#2}{#3}{#4}{#5}}
     247\def\@itemV@first#1#2#3#4#5{%
     248    \def\vers{V\the\verscnt}%
     249    \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
     250    \global\def\librable@table@print@addon{\hypertarget{\name}{}}%
     251    \gdef\livrableEndDate{#2}%
     252    \gdef\livrableType{#3}%
     253    \gdef\livrableLeader{#4}%
     254    \def\itemV{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemV@next}%
     255    \def\itemL{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemL@next}%
     256    \writeganttinfo{#1}{#2}{none}{#4}{#3}{#5}%
     257    \futurelet\nexttok\@livrable@desc@box@start@eatCR%
     258}
     259% \parskip0pt \topsep0pt \parsep0pt \itemsep0pt \partopsep0pt
     260
     261\def\@itemL@next#1#2#3#4#5#6{\global\@livrable@table@MustBeClosed@after@true\livrable@print@table\@itemL@first{#1}{#2}{#3}{#4}{#5}{#6}}
     262\def\@itemL@first#1#2#3#4#5#6{%
     263    \def\vers{VF}%
     264    \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
     265    \global\def\librable@table@print@addon{\hypertarget{\name}{}\hypertarget{\expandafter\@@novers\name\eoa}{}}%
     266    \gdef\livrableEndDate{#2}%
     267    \gdef\livrableType{#3}%
     268    \gdef\livrableLeader{#4}%
     269    \def\itemV{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemV@next}%
     270    \def\itemL{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemL@next}%
     271    \writeganttinfo{#1}{#2}{#6}{#4}{#3}{#5}%
     272    %\gdef\baselinestretch{2.50}XXX\\%
     273    \global\@livrable@table@MustBeClosed@true
     274    \futurelet\nexttok\@livrable@desc@box@start@eatCR%
     275}
     276
     277\newenvironment{livrable}{%
     278 \newcount\verscnt\verscnt=1
     279 \livrablecnt0
     280 \def\livrableTableDef{\begin{tabular}{|p{3.5em}|c|c|c|p{.625\linewidth}|}\hline}
    205281 \ifvmode \else\par\fi
    206    
    207  \def\itemV##1##2##3##4##5{%
    208     \ifIsLivrableStarted
    209         \global\advance\verscnt1
    210     \else
    211         \global\advance\livrablecnt1
    212         \global\verscnt1
    213     \fi
    214     \def\vers{V\the\verscnt}
    215     \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
    216     \hypertarget{\name}{}%
    217     \writeganttinfo{##1}{##2}{none}{##4}{##3}{##5}
    218     \\\hline
    219     \ifLivrableTopLine
    220       \ifIsLivrableStarted\else\hline\hline\fi
    221     \else
    222       \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi
    223     \fi
    224     \global\LivrableTopLinefalse
    225     \global\IsLivrableStartedtrue
    226     %\global\LivrableStartfalse
    227     \livrableTableLine%
    228         {\textsc{\name}}%
    229         {\textsc{T0+##2}}%
    230         {\textsc{##3}}%
    231         {\textsc{##4}}%
    232  }
    233  \def\itemL##1##2##3##4##5##6{%
    234     \ifIsLivrableStarted
    235         %\global\advance\verscnt1
    236     \else
    237         \global\advance\livrablecnt1
    238         %\global\verscnt1
    239     \fi
    240     \def\vers{VF}
    241     \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
    242     \hypertarget{\name}{}%
    243     \hypertarget{\expandafter\@@novers\name\eoa}{}%
    244     \writeganttinfo{##1}{##2}{##6}{##4}{##3}{##5}
    245     \\\hline
    246     \ifLivrableTopLine
    247       \ifIsLivrableStarted\else\hline\hline\fi
    248     \else
    249       \ifIsLivrableStarted\else\end{tabular}\\\livrableTableDef\fi
    250     \fi
    251     \global\LivrableTopLinefalse
    252     \global\IsLivrableStartedfalse
    253     %\global\LivrableStartfalse
    254     \livrableTableLine%
    255         {\textsc{\name}}%
    256         {\textsc{T0+##2}}%
    257         {\textsc{##3}}%
    258         {\textsc{##4}}%
    259  }
    260  \def\OtherPartner##1##2##3##4{{%
    261     \let\xcoach\relax
    262     \let\xcoachplus\relax
    263     \let\irisa\relax    \let\Sirisa\relax
    264     \let\lip\relax      \let\Slip\relax
    265     \let\tima\relax     \let\Stima\relax
    266     \let\ubs\relax      \let\Subs\relax
    267     \let\upmc\relax     \let\Supmc\relax
    268     \let\altera\relax   \let\Saltera\relax
    269     \let\bull\relax     \let\Sbull\relax
    270     \let\thales\relax   \let\Sthales\relax
    271     \let\mds\relax     \let\Smds\relax
    272     \immediate\write\ganttdata{%
    273       L=0 T=\the\taskcnt\space S=\the\subtaskcnt\space%
    274       D=\the\livrablecnt\space BM=##1 EM=##2 R=##4 PART={##3} TITLE=%
    275     }
    276  }}
    277 % \begin{small}
    278  \livrableTableDef
    279  \livrableTableTopLine
    280  %\begin{tabular}{|c|c|c|c|p{.55\linewidth}|}\hline%
    281  %\makebox[3.5em]{number} & \makebox[1.5em]{date} & type & resp. & description
    282 }
    283 {\\\hline\end{tabular}\\%
    284 %\end{small}\\%
    285 }
    286 
    287 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    288 \catcode`\@=12
    289 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     282\def\OtherPartner##1##2##3##4##5{{%
     283\let\xcoach\relax%
     284\let\xcoachplus\relax%
     285\let\irisa\relax\let\Sirisa\relax%
     286\let\lip\relax\let\Slip\relax%
     287\let\tima\relax\let\Stima\relax%
     288\let\ubs\relax\let\Subs\relax%
     289\let\upmc\relax\let\Supmc\relax%
     290\let\altera\relax\let\Saltera\relax%
     291\let\bull\relax\let\Sbull\relax%
     292\let\thales\relax\let\Sthales\relax%
     293\let\mds\relax\let\Smds\relax%
     294\immediate\write\ganttdata{%
     295  L=0 T=\the\taskcnt\space S=\the\subtaskcnt\space%
     296  D=\the\livrablecnt\space BM=##1 EM=##2 R=##4 PART={##3} TITLE=%
     297}%
     298}##5}
     299 \let\itemV\@itemV@first
     300 \let\itemL\@itemL@first
     301 \@livrable@firsttable@true
     302 \@livrable@table@MustBeOpened@true
     303 \@livrable@table@MustBeClosed@false
     304 \@livrable@table@MustBeClosed@after@false
     305 \def\@hypertarget@cor{0pt}
     306}{%
     307 \end{minipage}\end{lrbox}\global\setbox\livrable@box=\copy\livrable@box%
     308 \@livrable@table@MustBeClosed@true\livrable@print@table%
     309}
     310
     311%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

  • anr/section-consortium-people.tex

    r303 r304  
    5454
    5555\peopletabularentry{\upmc}
    56 responsible & Greiner     & Alain       & professor           & SOC ...     & 13  & Expertise in MPSoC design, virtual prototyping, micro-architecture.
     56responsible & Greiner     & Alain       & professor           & SOC         & 12  & Expertise in MPSoC design, virtual prototyping, micro-architecture.
    5757                                                                                    Responsible of Task-2. Participation to Task-3/6. \\\hline
    58 member      & Aug\'{e}    & Ivan        & assistant professor & HLS SOC HPC & 13  & Expertise in HLS, software development, kernel, SoC design, micro-architecture.
     58member      & Aug\'{e}    & Ivan        & assistant professor & HLS SOC HPC & 16  & Expertise in HLS, software development, kernel, SoC design, micro-architecture.
    5959                                                                                    Responsible of Task-3. Participation to Task-2/5/6/8. \\\hline
    6060                                       

  • anr/section-project-task-schedule.tex

    r300 r304  
    1414\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
    1515\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
    16 \immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
     16\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=27}
    1717%\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
    1818\def\ganttlabelstyle#1{\begin{small}\hyperlink{#1}{#1}\end{small}}
    … …  
    4949%The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
    5050Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
    51 $T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent
     51$T0+6$, $T0+12$, $T0+18$ and $T0+27$ that are rendez-vous points of the precedent
    5252deliverables.
    5353\begin{description}
    54 \item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
     54  \item[Milestone 1 ($T0+6$)]
     55    Specification of COACH inputs, of the \xcoach format and of
    5556    the demonstatrors as a reference software.
    56 \item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
    57     written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
     57  \item[Milestone 2 ($T0+12$)]
     58    The first COACH release. At this step the demonstrators are
     59    written in the COACH input format. This COACH release allows to prototype
     60    and to generate the FPGA-SoC.
    5861    The main restrictions are:
    5962    1) Only the neutral architectural template is supported,
    … …  
    6164    3) Enhanced communication schemes are not available.
    6265    4) ASIP compilation flow is not available.
    63 \item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
    64     features are availables. A preliminary version of the ASIP synthesis flow is supported, for a
    65    simple extensible MIPS model. The main restriction is that COACH can not yet
    66    generate FPGA-SoC for \altera and \xilinx architectural templates.
     66  \item[Milestone 3 ($T0+18$)]
     67    The second COACH release. At this step most of the COACH features are available.
     68    A preliminary version of the ASIP synthesis flow is supported, for a
     69    simple extensible MIPS model. The main restriction is that COACH can not yet
     70    generate FPGA-SoC for \altera and \xilinx architectural templates.
    6771    The others restriction is that the HAS tools are not yet fully operational.
    68 \item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
    69     supported.
    70     The main restriction are:
    71     1) The backend HAS tools have not been yet enhanced,
    72     2) Dynamic partial reconfiguration is not supported,
    73     3) NIOS processor instruction set extension is supported, but only for user specified patterns.
     72\item[Milestone 4 ($T0+27$)]
     73    The pre-release of the COACH project. The full design flow is supported.
     74    The main restrictions are:
     75    1) Automatic frequency calibration of coprocessor is not available.
     76    2) Automatic HPC set up is not yet available.
     77    3) NIOS processor instruction set extension is supported, but only for user
     78    specified patterns.
     79    4) GAUT enhencements are not available.
    7480\item[Final Release ($T0+36$)]
    75        
     81
    7682\end{description}
    77 This organisation allows the project to globally progress step by step mixing development
    78 and demonstrator deliverables.
    79 Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
    80 at the integration phase is significantly reduced.
     83This organisation allows the project to globally progress step by step mixing
     84development and demonstrator deliverables.
     85Hence, demonstrator feed-back will arrive early and so the risk to point out
     86incompatibility at the integration phase is significantly reduced.
    8187\par
    8288The risks that have been identified at the beginning of the project are the following:
    8389\begin{description}
    84 \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
    85         Partners have to agree on a convenient exchange format for all tools involved.
    86         Because all the HAS tools rely on it, the \xcoach format specification is a
    87     crucial step. There are no work-around but as mentionned in
    88     section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
    89         for a full year and a preliminary document already exists.
     90  \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
     91    Partners have to agree on a convenient exchange format for all tools involved.
     92    Because all the HAS tools rely on it, the \xcoach format specification is a
     93    crucial step.
     94    There are no work-around but as mentionned in section~\ref{xcoach-problem}
     95    (page~\pageref{xcoach-problem}) the five academic partners have worked on it
     96    for a full year and a preliminary document already exists.
    9097%\item[\xcoachplus format (\novers{\specXcoachDoc},
    9198%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
    … …  
    93100%    By centralizing the coprocessor generation, it guarantees their functioning
    94101%    independently of the used HAS tools.
    95 %       Our experience with UGH and GAUT give us confidence in the succes of this
    96 %       task.
    97 \item[Virtual prototyping of \altera \& \xilinx architectural templates ({\NOVERScsgImplementation})]
    98      The SoCLib component library contains several SystemC models used for the virtual
    99      prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
    100      Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
    101      If the workload of this simulation model development is too important, virtual prototyping
    102          of those architectural templates will not be directly supported.
    103          The three architectural templates being quite similar, the virtual
    104          prototyping will use the neutral architectural template.
    105 \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
    106      If one of these tasks is impossible or too important or leads to inefficiency,
    107      it will be abandoned.
    108      In this case, the neutral architectural template will not be available for HPC and
    109      a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
    110      virtual prototyping.
     102%   Our experience with UGH and GAUT give us confidence in the succes of this
     103%   task.
     104  \item[Virtual prototyping  ({\NOVERScsgImplementation})]
     105    In this project, only the virtual prototyping of the neutral architectural
     106    template is supported.
     107    We think that this restriction is not a serious problem.
     108    Indeed the \altera \& \xilinx architectural templates being architecturally close of
     109    the neutral architectural template, an efficient software/hardware partition
     110    on the neutral architectural template is also an efficient on the other
     111    architectural templates.
     112    The project will allow to verify experimentally this assumption.
     113%  \item[Virtual prototyping of \altera \& \xilinx architectural templates
     114%    ({\NOVERScsgImplementation})]
     115%    The SoCLib component library contains several SystemC models used for the
     116%    virtual prototyping of the \altera and \xilinx architectural templates
     117%    (NIOS and Microblaze processor cores).
     118%    Nevertheless, at this time we do not know how many IP cores SystemC
     119%    simulation models have to be developped.
     120%    If the workload of this simulation model development is too important,
     121%    virtual prototyping of those architectural templates will not be directly
     122%    supported.
     123%    The three architectural templates being quite similar, the virtual
     124%    prototyping will use the neutral architectural template.
     125  \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
     126    These bridges may decrease the efficiency of the \altera \& \xilinx
     127    architectural templates.
     128    Developing the communication components (MWMR) for the AVALON and PLB buses
     129    will correct this problem.
     130%    If one of these tasks is impossible or too important or leads to inefficiency,
     131%    it will be abandoned.
     132%    In this case, the neutral architectural template will not be available for HPC and
     133%    a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
     134%    virtual prototyping.
    111135\end{description}
    112136\parlf

  • anr/section-ressources.tex

    r290 r304  
    187187    non-permanent personnels.
    188188    The detail by deliverables is given in figure~\ref{table-livrables-2}.
    189     The non-permanent personnels costs represent 50\% of the personnal costs.
     189    The non-permanent personnels costs (24 \hommemois) represent 46\% of the personnal costs.
    190190    The requested funding for non permanent personnels is 79\% of the total ANR
    191191    requested funding.

  • anr/task-backbone.tex

    r300 r304  
    8080        developers of HAS tools suggested.
    8181    \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{7:3:0}
    82         \OtherPartner{0}{18}{\Supmc}  {.5:0:0}
    83         \OtherPartner{0}{18}{\Stima}  {.5:0:0}
     82        \OtherPartner{0}{18}{\Supmc}  {.5:.5:0}
     83        \OtherPartner{0}{18}{\Stima}  {.5:.5:0}
    8484        \setMacroInAuxFile{specXcoachDoc}
    8585        Last release of XML specification of the \xcoach format enhanced with
    … …  
    101101        The first release of the software tool X2SC  that translates \xcoachplus
    102102        description to CABA and TLM-DT SystemC module.
    103     \itemL{18}{24}{x}{\Supmc}{X2SC tool}{0:1.5:0}
     103    \itemL{18}{27}{x}{\Supmc}{X2SC tool}{0:1:.5}
    104104        \setMacroInAuxFile{specXcoachToSystemC}
    105105        Final release of the former software (\specXcoachToSystemCI).
    … …  
    108108        The first release of the software tool X2VHDL that translates \xcoachplus
    109109        description to synthesizable VHDL description.
    110     \itemL{18}{24}{x}{\Subs}{X2VHDL tool}{0:3:0}
     110    \itemL{18}{27}{x}{\Subs}{X2VHDL tool}{0:2:1}
    111111        \setMacroInAuxFile{specXcoachToVhdl}
    112112        Final release of the former software (\specXcoachToVhdlI).

  • anr/task-backend.tex

    r300 r304  
    3939    \itemV{12}{18}{x}{\Stima}{UGH integration}
    4040        UGH release that interprets the task communication API.
    41     \itemV{18}{24}{x}{\Supmc}{UGH integration}
     41    \itemV{18}{27}{x}{\Supmc}{UGH integration}
    4242        UGH release that writes \xcoachplus format.
    43     \itemL{24}{36}{x}{\Stima}{UGH integration}{3:3:1}
    44         \OtherPartner{0}{12}{\Supmc}{1:3:1}
     43    \itemL{27}{36}{x}{\Stima}{UGH integration}{3:3:1}
     44        \OtherPartner{0}{12}{\Supmc}{1:2.5:1}
    4545        UGH release taking into account demonstrator's feedback.
    4646%
    … …  
    4949    \itemV{12}{18}{x}{\Subs}{GAUT integration}
    5050        GAUT release that interprets the task communication API.
    51     \itemV{18}{24}{x}{\Subs}{GAUT integration}
     51    \itemV{18}{27}{x}{\Subs}{GAUT integration}
    5252        GAUT release that writes \xcoachplus format.
    53     \itemL{24}{36}{x}{\Subs}{GAUT integration}{6:6:3}
     53    \itemL{27}{36}{x}{\Subs}{GAUT integration}{6:6:3}
    5454        \setMacroInAuxFile{gautFinal}
    5555        GAUT release taking into account demonstrator's feedback.
    … …  
    6868    \itemV{0}{12}{d}{\Supmc}{Frequency calibration}
    6969        A document describing the set up of the coprocessor frequency calibration.
    70     \itemV{12}{24}{x}{\Supmc}{Frequency calibration}
     70    \itemV{12}{27}{x}{\Supmc}{Frequency calibration}
    7171        A VHDL description of hardware added to the coprocessor to enable the calibration.
    72     \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{1:1:4}
     72    \itemL{27}{33}{x}{\Supmc}{Frequency calibration}{1:1:4}
    7373        \setMacroInAuxFile{freqCalibrationVhdl}
    7474        The frequency calibration software consists of a driver in the FPGA-SoC operating
    … …  
    7878\subtask{GAUT enhancement}
    7979    \begin{livrable}
    80     \itemV{18}{24}{d}{\Subs}{GAUT enhancement}
     80    \itemV{18}{27}{d}{\Subs}{GAUT enhancement}
    8181        Specification of GAUT enhancements.
    8282        The first ones is to support new constraints and objectives.
    … …  
    8484        able to use synthesis feed-back informations in order to explore the
    8585        design space and to generate optimized architectures.
    86     \itemL{24}{36}{x}{\Subs}{GAUT enhancement}{0:4:4}
     86    \itemL{27}{36}{x}{\Subs}{GAUT enhancement}{0:4:4}
    8787        Integration of these enhancements into the final GAUT release
    8888        ({\gautFinal} deliverable).

  • anr/task-csg.tex

    r300 r304  
    1010\begin{itemize}
    1111  \item The development of the synthesizable models required for the connection
    12         of the coprocessors on the platform bus (2 bridges).
     12    of the coprocessors on the platform bus (2 bridges).
    1313  \item The configuration and the development of drivers of the operating
    14         systems (Board Support Package, HAL).
     14    systems (Board Support Package, HAL).
    1515  \item The CSG software that generates the SystemC simulators for prototyping
    16         and the FPGA-SoC system including its bitstream and software executable code.
     16    and the FPGA-SoC system including its bitstream and software executable code
     17    (see Figure~\ref{architecture-csg} and ~\ref{architecture-hls}).
    1718\end{itemize}
    1819A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
    … …  
    2425\subtask{Bridge implementation}
    2526    This \ST deals with the development of the synthesizable models required for
    26         the connection of the coprocessors on the platform bus.
     27    the connection of the coprocessors on the platform bus.
    2728    \begin{livrable}
    28     \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:2:5}
     29    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3}
    2930        \setMacroInAuxFile{hpcPlbBridge}
    3031        The synthesizable VHDL description of a PLB/VCI bridge.
    31     \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:2:5}
     32    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3}
    3233        \setMacroInAuxFile{hpcAvalonBridge}
    3334        The synthesizable VHDL description of an AVALON/VCI bridge.
    3435    \end{livrable}
    3536\subtask{OS setup}
    36         This \ST consists of the configuration of the SocLib DNA operating
     37    This \ST consists of the configuration of the SocLib DNA operating
    3738    system and the development of drivers for the hardware architectural templates.
    3839    For the \altera and \xilinx architectural templates, the OS must also be ported on
    … …  
    6263        architectural template, and an integration of an HLS tools
    6364        but only for SystemC prototyping.
    64     \itemV{18}{24}{x}{\Supmc}{CSG}
     65    \itemV{18}{27}{x}{\Supmc}{CSG}
    6566        This release extends CSG to FPGA-SoC generation for the \xilinx and
    66                 \altera architectural template.
    67     \itemL{24}{36}{x}{\Supmc}{CSG tool}{5:3:2}
    68         \OtherPartner{0}{36}{\Stima}{0:6:0}
    69         \OtherPartner{0}{36}{\Smds}{0:6:0}
    70                 \setMacroInAuxFile{csgImplementation}
    71         \mustbecompleted{TIMA : integration d'OS dans CSG, en particulier DNA}
     67        \altera architectural template.
     68    \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3}
     69        \OtherPartner{0}{36}{\Stima}{1:3:2}
     70        \OtherPartner{0}{36}{\Smds}{1:3:3}
     71        \setMacroInAuxFile{csgImplementation}
    7272        Final release of CSG enhanced by the demonstrator's feedback.
     73        \\
     74        The work will be split between the partner as follow: 1) \Supmc will
     75        design the core of CSG, 2) \Stima will design the part concerning the
     76        generation of system software and the configuration of CSG to other OS.
     77        3) \Smds will focus to interface CSG to the IP-XACT format for
     78        generating IP integrable into a IP-XACT flow such as socket and to
     79        configure CSG to new IP or plate-form.
    7380    \end{livrable}
    7481\end{workpackage}

  • anr/task-demonstrator.tex

    r300 r304  
    8686    3) the design time from a high level description.
    8787    \begin{livrable}
    88       \itemV{18}{24}{d+x}{\Smds}{Evaluation}
     88      \itemV{18}{27}{d+x}{\Smds}{Evaluation}
    8989        This deliverable written by \Smds, \Sbull and \Sthales is a document
    9090        that synthesizes the results got for the demonstrators
    … …  
    9292        \NOVERStrtSpearde, \NOVERSmdsAppSpecification)
    9393        using the COACH milestone of T0+18.
    94       \itemV{24}{30}{d+x}{\Smds}{Evaluation}
    95         Same as former but for the milestone of T0+24.
     94      \itemV{27}{30}{d+x}{\Smds}{Evaluation}
     95        Same as former but for the milestone of T0+27.
    9696      \itemL{30}{36}{d+x}{\Smds}{Evaluation}{0:5:5}
    9797        \OtherPartner{18}{36}{Sbull}{0:5:5}
    … …  
    104104        \NOVERStrtAppSpecification) will be provide.
    105105    \end{livrable}
    106 %% GROUPED ABOVE%%     \begin{livrable}
    107 %% GROUPED ABOVE%%       \itemV{24}{30}{d+x}{\Smds}{\mds evaluation}
    108 %% GROUPED ABOVE%%         This deliverable is a document describing the result got for the application
    109 %% GROUPED ABOVE%%         (\mdsAppSpecification) using COACH milestone of T0+24.
    110 %% GROUPED ABOVE%%       \itemL{30}{36}{d+x}{\Smds}{\mds evaluation}{0:5:5}
    111 %% GROUPED ABOVE%%         This deliverable is a document that validates and evaluates COACH (final release)
    112 %% GROUPED ABOVE%%         for the \mds demonstrators (\mdsAppSpecification).
    113 %% GROUPED ABOVE%% %
    114 %% GROUPED ABOVE%%       \itemV{24}{30}{d+x}{\Sbull}{\bull evaluation}
    115 %% GROUPED ABOVE%%         This deliverable is a document describing the result got for the application
    116 %% GROUPED ABOVE%%         (\bullAppSpecification) using COACH milestone of T0+24.
    117 %% GROUPED ABOVE%%       \itemL{30}{36}{d+x}{\Sbull}{\bull evaluation}{0:5:5}
    118 %% GROUPED ABOVE%%         This deliverable is a document that validates and evaluates COACH (final release)
    119 %% GROUPED ABOVE%%         for the \bull demonstrators (\bullAppSpecification).
    120 %% GROUPED ABOVE%% %
    121 %% GROUPED ABOVE%%       \itemV{18}{24}{d+x}{\Sthales}{\thales evaluation}
    122 %% GROUPED ABOVE%%         This deliverable is a document describing the result got for the application
    123 %% GROUPED ABOVE%%         (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18.
    124 %% GROUPED ABOVE%%         The updated code of the application will be also provide.
    125 %% GROUPED ABOVE%%       \itemV{24}{30}{d+x}{\Sthales}{\thales evaluation}
    126 %% GROUPED ABOVE%%         This deliverable is a document describing the result got for the application
    127 %% GROUPED ABOVE%%         (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
    128 %% GROUPED ABOVE%%         The updated code of the application will be also provide.
    129 %% GROUPED ABOVE%%       \itemL{30}{36}{d+x}{\Sthales}{\thales evaluation}{0:5:5}
    130 %% GROUPED ABOVE%%         This deliverable is a document that validates and evaluates COACH (final release)
    131 %% GROUPED ABOVE%%         for the \thales demonstrators (\trtAppSpecification).
    132 %% GROUPED ABOVE%%         The updated code of the application will be also provide.
    133 %% GROUPED ABOVE%%     \end{livrable}
    134106
    135107\end{workpackage}

  • anr/task-dissemination.tex

    r302 r304  
    4848        task graph can be obtained.
    4949        \end{description}
    50     \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.5}
    51         \OtherPartner{30}{36}{\Smds}{0:0:2}
     50    \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.0}
     51        \OtherPartner{30}{36}{\Smds}{1.5:0:1}
    5252        The final release of the tutorial. It will be completed with sections
    5353        that illustrate:
    … …  
    6363  \subtask{Reference user manuals} 
    6464   \begin{livrable}
    65    \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:1:0}
     65   \itemL{21}{27}{d}{\Stima}{CSG User manual}{0:.5:1}
    6666        This user manual shows how to generate a complete HW/SW system by using CSG tool.
    67     \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:1:0}
     67    \itemL{21}{27}{d}{\Slip}{HAS front-end user manual}{0:.5:1}
    6868        This user manual shows how to apply loop transformations to a task.
    69     \itemL{18}{36}{d}{\Sirisa}{ASIP user manual}{0:1:1}
     69    \itemL{21}{27}{d}{\Sirisa}{ASIP user manual}{0:1:1}
    7070        This user manual shows how to customize a processor to obtain an ASIP.
    71     \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0}
     71    \itemL{21}{27}{d}{\Subs}{HLS user manual}{0:.5:1}
    7272        This user manual shows how a task can be synthesized by using UGH and GAUT  tools.
    7373      \OtherPartner{12}{36}{\Subs}{0:2:2}
    74     \itemL{18}{36}{d}{\Smds}{Magillem framework user manual}{0:1:1}
     74    \itemL{21}{27}{d}{\Smds}{Magillem framework user manual}{0:1:1}
    7575        This user manual describes how to use COACH within the IP-XACT based Magillem tool suite.
    7676   \end{livrable}

  • anr/task-frontend.tex

    r291 r304  
    3131        custom instructions are specified by the user, and then automatically extracted (when
    3232        beneficial) from the application intermediate representation.
    33       \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0}
     33      \itemL{18}{27}{x}{\Sirisa}{ASIP compilation flow}{0:6:3}
    3434        In this second version, the software will also be able to automatically identify
    3535        interesting pattern candidates in the application code, and use them as custom
    … …  
    5050      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
    5151      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
    52       \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
     52      \itemL{18}{27}{h}{\Sirisa}{VHDL for extensible MIPS}{9:9:3}
    5353      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
    5454      its instruction set extensions}
    55       \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
     55      \itemL{27}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
    5656      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
    5757      the different approaches}

  • anr/task-hpc.tex

    r300 r304  
    4141        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
    4242        This library is dedicated to help the end-user to partition an application for HPC.
    43       \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:2:0}
    44         \setMacroInAuxFile{hpcCommLinux}
    45         The PC part of the HPC communication API that communicates with the FPGA-SOC, a
    46         library and a LINUX module.
    47       \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
    48         \setMacroInAuxFile{hpcDnaDriver}
    49         The FPGA-SoC part of the communication API (DNA driver).
     43      \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5}
     44        \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0}
     45        \OtherPartner{21}{27}{\Sbull}{0:0.5:0.5}
     46        \setMacroInAuxFile{hpcForLinux}
     47        This deliverable groups all the software components to implement the
     48        HPC communication API (\NOVERShpcCommApi).
     49        \Supmc will develop the Linux part (a C library and a LINUX module),
     50        \Stima will develop the FPGA-SoC part (a DNA driver),
     51        \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification).
    5052    \end{livrable}
    5153%
    … …  
    5456    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
    5557    \begin{livrable}
    56     \itemL{12}{24}{h}{\Supmc}{PCI/X traffic generator}{0:1:0}
     58    \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1}
    5759        The SystemC description of a component that generates PCI/X traffic. It is
    5860        required to prototype FPGA-SoC dedicated to HPC.

  • anr/task-management.tex

    r296 r304  
    2828        levels: progress monitoring, record keeping, meeting organization, review
    2929        organization, the writing of the review reports.
    30     \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5}
    31         \OtherPartner{0}{36}{\Supmc}  {.5:.5:.5}
    32         \OtherPartner{0}{36}{\Subs}   {.5:.5:.5}
    33         \OtherPartner{0}{36}{\Stima}  {.5:.5:.5}
    34         \OtherPartner{0}{36}{\Slip}   {.5:.5:.5}
    35         \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5}
    36         \OtherPartner{0}{36}{\Sthales}{.5:.5:.5}
    37         \OtherPartner{0}{36}{\Sbull}  {.5:.5:.5}
     30    \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5}%
     31        \OtherPartner{0}{36}{\Supmc}  {.5:.5:.5}%
     32        \OtherPartner{0}{36}{\Subs}   {.5:.5:.5}%
     33        \OtherPartner{0}{36}{\Stima}  {.5:.5:.5}%
     34        \OtherPartner{0}{36}{\Slip}   {.5:.5:.5}%
     35        \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5}%
     36        \OtherPartner{0}{36}{\Sthales}{.5:.5:.5}%
     37        \OtherPartner{0}{36}{\Sbull}  {.5:.5:.5}%
    3838        Project management at the partner level. It includes mainly the progress
    3939        monitoring, the record keeping the participation to the project meetings
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