Changeset 307 for anr


Ignore:
Timestamp:
Jan 13, 2011, 7:14:58 PM (14 years ago)
Author:
coach
Message:

Modifications EV: inputs MDS

Location:
anr
Files:
9 edited

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  • anr/anr.tex

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    22
    33\usepackage[french,english]{babel}
    4 \usepackage[utf8x]{inputenc}
     4\usepackage[utf8]{inputenc}
    55\usepackage{times}
    66\usepackage[T1]{fontenc}

  • anr/section-2.tex

    r297 r307  
    3333      communication infrastructure.
    3434\end{enumerate}
    35 The proposed design flow starts from a high level description of the application, specified as a set of
    36 parallel tasks written in C, without any assumption on the hardware or software implementation
    37 of these tasks. It lets the system
    38 designer in charge of expressing the coarse grain parallelism of the application, gives the designer
    39 the possibility to explore various mapping of the application on the selected template architecture,
    40 and offers a high predictability of results with respect to cost and performance objectives.
    41 \\
    42 When this interactive, system level, design space exploration is completed (converging to
    43 a specific mapping on a specific version of the selected architectural template), the rest of the flow
    44 is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
    45 code for the software running on the embedded processors, and the bit-stream to program the target FPGA
    46 will be automatically generated by the COACH tools.
    47 %
    48 \parlf
    49 The strength of the COACH approach is the strong integration of the high-level synthesis tools
    50 in a platform based design flow supporting virtual prototyping and design space exploration.
    51 Most building blocks already exist (resulting from previous projects): the GAUT
    52 or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
    53 the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
    54 as well as the SoCLib library of SystemC simulation models.
    55 They must now be enhanced and integrated in a consistent design flow: this will
    56 be done in Magillem framework thanks to the IP-XACT standard.
    57 %The five academic laboratories worked very closely during more than one year (one monthly meeting
    58 %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
    59 %those various technologies, and to define the detailed architecture of the proposed design flow.
    60 %%%
     35%The proposed design flow starts from a high level description of the application, specified as a set of
     36%parallel tasks written in C, without any assumption on the hardware or software implementation
     37%of these tasks. It lets the system
     38%designer in charge of expressing the coarse grain parallelism of the application, gives the designer
     39%the possibility to explore various mapping of the application on the selected template architecture,
     40%and offers a high predictability of results with respect to cost and performance objectives.
     41%\\
     42%When this interactive, system level, design space exploration is completed (converging to
     43%a specific mapping on a specific version of the selected architectural template), the rest of the flow
     44%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
     45%code for the software running on the embedded processors, and the bit-stream to program the target FPGA
     46%will be automatically generated by the COACH tools.
     47%%
     48%\parlf
     49%The strength of the COACH approach is the strong integration of the high-level synthesis tools
     50%in a platform based design flow supporting virtual prototyping and design space exploration.
     51%Most building blocks already exist (resulting from previous projects): the GAUT
     52%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
     53%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
     54%as well as the SoCLib library of SystemC simulation models.
     55%They must now be enhanced and integrated in a consistent design flow: this will
     56%be done in Magillem framework thanks to the IP-XACT standard.
     57%%The five academic laboratories worked very closely during more than one year (one monthly meeting
     58%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
     59%%those various technologies, and to define the detailed architecture of the proposed design flow.
     60%%%%
    6161\parlf
    6262In HPC (High Performance Computing), the targeted application is an existing one
    … …  
    6969This will allow SMEs to enter HPC market for the applications that are
    7070unadapted to the current GPU based solutions.
     71\parlf
     72Coach generates SoC which is part of larger system. Thus it's important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC.
     73\begin{center}\begin{minipage}{.8\linewidth}\textit{
     74The third objective of COACH is to facilitate the integration of generated SoC in global system design flow.
     75}\end{minipage}\end{center}
    7176%%%

  • anr/section-consortium-desc.tex

    r293 r307  
    169169\subsubsection{\mdslong}
    170170
    171 \mustbecompleted{A COMPLETER: Emmanuel ....}
     171Magillem Design Services has been established by a team of seasoned engineers and a
     172group of business angels in the fall of 2006. The company has inherited Magillem, a
     173robust and innovative technology worth 120 man years. The Magillem environment is
     174dedicated to the design, verification and flow management of complex HW/SW based on IP-XACT.
     175In the service area, we audit the existing industrial flows and propose a work plan to
     176adapt them to IP-XACT, we validate and verify the full compatibility of tools interfaces
     177into a flow testbench, we test the IP deliverables against a benchmark for compliance
     178using our IP-XACT packager, and check IP integration properties onto a test system.
     179Magillem's tools are used in the most advanced production flows of integrated circuit
     180manufacturers (ST, NXP, TI, Qualcomm, etc.) and are linked with the research work of
     181the best laboratories of the domain (LIP6, TIMA, Fhg, OFFIS, etc.). Our participation
     182to leading European collaborative projects (e.g. IST COMPLEX, SPRINT, ICODES, etc.)
     183allow us to maintain a high level of innovation around our core technology: SoC design
     184methodologies at ESL, design and verification in AMS domain, HW/SW co-design, safety
     185and security of systems.
     186Beyond this core technology domain, Magillem has evolved with the tool suite called
     187Revenge, answering to wider assembly issues for large heterogeneous systems.
    172188
    173189%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

  • anr/section-consortium-leader.tex

    r289 r307  
    33coordonner le projet.}
    44
    5 \mustbecompleted{EMANNUEL}
     5Emmanuel Vaumorin is responsible for research and development program at MDS. Since 2003,
     6he is managing the realization of work for more than 12 projects (IST, MEDEA+, CATRENE, ANR, FUI, etc.).
     7Emmanuel is contributing member in the IP-XACT working group of ACCELERA.
     8In 2002-2005, Emmanuel was project manager of the project SystemC'mantic in
     9the former call RNTL. The main onjective was to set up a design and verification environment
     10based on the new language SystemC and introducing new techniques of system level design.
     11The partners of this project were Thales, CEA-LIST, TIMA, LESTER.
     12This project has reached all its objectives in time and has been well ranked by the reviewer.
     13In 2002-2003 he was product manager for an ESL design and verification
     14environment based on SystemC. Emmanuel is graduated from the Conservatoire
     15National des Arts et M\'etiers in the field of digital electronics for communications.
     16Emmanuel is one of the co-founders of Magillem.

  • anr/section-consortium-people.tex

    r306 r307  
    3232
    3333\peopletabularentry{\mds}           
    34 coordinator & Vaumorin    & Emannuel    & ...                 & ...         & ... & ... \\\hline
    35 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
    36                                        
     34coordinator & Vaumorin    & Emannuel    & Strategic Project Manager & ESL   & ... & Project leader \\\hline
     35...         & Spasevski   & Cyril       & CTO                 & EDA         & ... & Technical specifications \\\hline
     36...         & Guntz       & St\'ephane  & VP of Engineering   & EDA         & ... & Demonstrator specification and management \\\hline                       ...         & Lucas       & Ronan       &         & EDA         & ... & Tools and demonstrator implementation \\\hline       
     37
    3738\peopletabularentry{\irisa}
    3839...         & Derien      & Steven      & ...                 & ...         & ... & ... \irisa \\\hline

  • anr/section-etat-de-art.tex

    r289 r307  
    221221an active research subject.
    222222
     223\subsubsection{SoC design flow automation using IP-XACT}
     224
     225IP-XACT is an XML based open standard defined by the Accellera consortium.
     226This non-profit organisation provides a unified set of high quality IP-XACT
     227specifications for documenting IP using meta-data. This meta-data will be
     228used for configuring, integrating, and verifying IP in advanced SoC design
     229and interfacing tools using TGI (Tight Generator Interface is a software API)
     230that can be used to access design meta-data descriptions of complete system designs.
     231The specification for the schema is tailored to the requirements of the industry,
     232and focused on enabling technologies for the efficient design of electronic
     233systems from concept to production. The last IEEE 1685 release of IP-XACT incorporates
     234both RTL and TLM (transaction level modelling) capabilities. Thus it can be used to
     235package IP portfolios and describe their assembly in complex hardware architectures.
     236These description files are the basis for tool interoperability and data exchange
     237through a common structured data management. Today more than two hundred companies
     238are members of the consortium and the board is incorporating top actors
     239(STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the
     240wide adoption by industry. Initiatives have already work for extending this standard
     241to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent
     242Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for
     243further releases.
     244
     245In IP-XACT the flow automation and data constistency is ensured by generators, which
     246are program modules that process IP-XACT XML data into something useful
     247for the design. They are key portable mechanism for encapsulating specialist design
     248knowledge and enable designers to deploy specialist knowledge in their design. It is
     249always possible to create generators in order to link several design or analysis tools
     250around a centric representation of metadata in IP-XACT. This kind of XML schema for
     251metadata management is a good solution for the federation of heterogeneous design domains
     252(models, tools, languages, methodologies, etc.).
     253
    223254%\subsubsection{High Performance Computing}
    224255%Accelerating high-performance computing (HPC) applications with field-programmable

  • anr/section-issues.tex

    r289 r307  
    66indicateurs de réduction de coûts, perspectives de marchés (champs
    77d’application, 
). Indicateurs des gains environnementaux, cycle de vie.}
    8 
    9 
     8%
     9\subsubsection*{Predominance of FPGA in the global electronic market}
    1010\begin{table}\leavevmode\center
    1111\begin{small}\begin{tabular}{|l|l|l|l|}\hline
    … …  
    3838Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
    3939volume markets.
    40 \parlf
     40%
     41\subsubsection*{FPGAs and Embedded Systems}
    4142Today, FPGAs become important actors in the computational domain that was originally dominated
    4243by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
    … …  
    5960%This boosts the developpment of automatic design tools and methodologies.
    6061%
    61 \parlf
     62\subsubsection*{FPGAs and High Performance Computing}
    6263Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
    6364Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
    … …  
    7071This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
    7172of FPGA-based solutions is limited by the lack of design automation.
    72 \\
    73 \\
     73%
     74\subsubsection*{Evolution of architectures}
     75Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C).
     76"Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic
     77products (eg. PDAs and nomad items) and even personal computers.
     78To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools.
     79
     80%
     81\subsubsection*{COACH's contribution to this evolution}
    7482Nowadays, there are no commercial or academic tools covering the whole design flow
    7583from the system level specification to the bitstream generation neither for embedded system design
    7684nor for HPC.
    77 
    78 %PC => IA et Alain
    79 %Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
    80 %Je le mets donc en commentaire
    81 
    82 %By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
    83 %parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
    84 %processor,  bus core, ...) as well as incorporate their own IP.
    85 %Designers can then generate a synthesized netlist, simulation test bench and custom
    86 %software library that reflect the hardware configuration.
    87 %Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
    88 %simulate the platform at a high design level (systemC).
    89 %In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
    90 %tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
    91 %PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
    92 %coprocessors from a C++ description.
    93 %Nevertheless, they can only deal with data dominated applications and they do not handle
    94 %the platform level.
    95 %Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
    96 %Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
    97 %Designers can design and simulate a system using MATLAB and Simulink. The tool will then
    98 %automatically generate synthesizable Hardware Description Language (HDL) code mapped to
    99 %\xilinx pre-optimized macro-cells.
    100 %However, this tool targets only DSP based algorithms.
    101 %\\
    102 %Consequently, a designer developping an embedded system needs to master four different
    103 %design environments:
    104 %\begin{enumerate}
    105 %  \item a virtual prototyping environment such as SoCLib for system level exploration,
    106 %  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
    107 %  from \xilinx) to define the hardware architecture,
    108 %  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
    109 %        coprocessor synthesis,
    110 %  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
    111 %\end{enumerate}
    112 %Furthermore, mixing these tools requires an important interfacing effort and this makes
    113 %the design process very complex and achievable only by designers skilled in many domains.
    114 
    11585\begin{center}\begin{minipage}{.9\linewidth}\textit{
    11686The aim of the COACH project is to integrate all these design steps into a single design framework
    11787and to allow \textbf{pure software} developpers to design embedded systems.
    11888}\end{minipage}\end{center}
    119 
    120 %PC => IA et Alain
    121 % le paragraphe suivant est coupé collé de la section suivante 2.2
    122 
    123 
    124 \parlf
     89%
    12590The COACH project proposes an open-source framework for mapping multi-tasks software applications
    12691on Field Programmable Gate Array circuits (FPGA).

  • anr/section-position.tex

    r297 r307  
    2323%on Field Programmable Gate Array circuits (FPGA).
    2424%%%
    25 \parlf
     25\subsubsection*{Positionning in regards with the economical and social context}
    2626COACH will contribute to build an open design and run-time
    2727environment, including communication middleware and tools to support
    … …  
    3737\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
    3838environment, suitable for co-operative and distributed development.
    39 \item \mustbecompleted{IP-XACT: .... MAGILLEM...}
     39\item Integration of the solutions and engines being developped into a state of the art SoC and system
     40design flow, using the IP-XACT IEEE 1685 standard.
    4041\end{itemize}
    4142COACH outcome will contribute to strengthen Europe's competitive position by developing
    … …  
    5152%%%
    5253\parlf\noindent
     54\subsubsection*{Positionning and continuity with other projects}
    5355The COACH project will benefit from a number of previous recent projects:
    5456\begin{description}
    … …  
    8890    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    8991    be able to validate the framework on real-life HPC applications.
    90   \item[SoCket]  \mustbecompleted{...... MAGILEM ......}
    91   \item[HOSPI]   \mustbecompleted{...... MAGILEM ......}
    92   \item[SoftSoc] \mustbecompleted{...... MAGILEM ......}
     92
     93  \item[SoCket]
     94    The design flow defined in this project targets the design of critical embedded systems.
     95    It covers important steps as system architecture exploration, and the definition of virtual
     96    prototypes at different levels of abstraction to support early embedded software development,
     97    verification of hardware blocks, and preparation of certification activities.
     98    COACH solutions and engines will be specified to be integrated into this standard flow.
     99    MDS, Thales TRT, TIMA are already collaborating in this project.
     100
     101  \item[HOSPI] 
     102     The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease
     103     the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description
     104     format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow.
     105
     106  \item[SoftSoC]
     107     TIMA and MDS are involved in this project, which aims at the standard definition and generation of Hardware Dependent Software layers of a system.
     108     Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. 
     109
    93110\end{description}
    94111%%%
    … …  
    125142    will be very useful as a front-end for HLS tools.
    126143  \item
    127     Regarding \mustbecompleted{.... MAGILLEM ... IP-XACT}
     144    Regarding industrial flow integration \mds will bring its strong expertise
     145    in IEEE 1685 (IP-XACT) standard. \mds team is involved and contributes actively
     146    to it since 2003 and Magillem tool suite is used for its validation. Magillem is used in
     147    industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales,
     148    Astrium, Thomson, etc. what guarantees a strong alignement on customers needs and enhance results exploitation.
     149
    128150\end{itemize}
    129151%%%
    130 \parlf\noindent
     152\subsubsection*{Relevance to the call axis}
    131153The COACH project totally fulfills the objectives of the axis 2 "METHODES,
    132154OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES".
    … …  
    163185quality and reducing the design time and the cost of synthesised cryptographic devices.
    164186\mustbecompleted{END-FIXME}
    165 \parlf
     187%
     188\subsubsection*{European and international positionning}
     189%
    166190Finally, it is worth to note that this project covers priorities defined by the commission
    167191experts in the field of Information Technolgies Society (IST) for Embedded

  • anr/task-demonstrator.tex

    r304 r307  
    7171%
    7272  \subtask{\mds use case}
    73     \mustbecompleted{\mds will use .................}
     73    The goal of the \mds demonstrator will be to experiment and validate the good integration
     74    of the COACH tools into an industrial SoC design flow for critical systems. This demonstrator will be based on
     75    the standard flow defined in the SoCket project and \mds will use a classical SoC platform
     76    based on the LEON processor and which simulation models are available for free (this will
     77    facilitate the further dissemination of the demonstrators to external prospects).
     78    The required prototypes of IP-XACT generators will be specified and implemented; they will be
     79    generic enough or at least customizable in order to be at the basis of the further deployement into
     80    actual design flows. The objectives of this demonstrator are the following:
     81\begin{itemize}
     82        \item Validate the IP-XACT packaging of the generated SoC
     83        \item Experiment the integration of the generated SoC into the top level (TLM or RTL) of a bigger system
     84        \item Bring a focus on flow capabilities for requirements traceability from system properties, down to sub-systems implementation
     85\end{itemize}
     86
    7487    \begin{livrable}
    75       \itemL{6}{18}{x}{\Smds}{Use case}{6:7:0}
     88      \itemL{0}{12}{d}{\Smds}{Use case}{6:7:0}
    7689        \setMacroInAuxFile{mdsAppSpecification}
    77         \mustbecompleted{Adaptation of ...}
     90        This deliverable is a document that specifies the demonstrator.
     91      \itemL{12}{24}{x}{\Smds}{\mds demonstrator}{4:0:0}
     92        This deliverable is the intermediate demonstrator specified in (\mdsAppSpecification).
     93      \itemL{24}{12}{x}{\Smds}{\mds demonstrator}{4:0:0}
     94        This deliverable is the final demonstrator specified in (\mdsAppSpecification).
    7895    \end{livrable}
    7996
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