Changeset 307 for anr/section-2.tex


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Timestamp:
Jan 13, 2011, 7:14:58 PM (13 years ago)
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coach
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Modifications EV: inputs MDS

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  • anr/section-2.tex

    r297 r307  
    3333      communication infrastructure.
    3434\end{enumerate}
    35 The proposed design flow starts from a high level description of the application, specified as a set of
    36 parallel tasks written in C, without any assumption on the hardware or software implementation
    37 of these tasks. It lets the system
    38 designer in charge of expressing the coarse grain parallelism of the application, gives the designer
    39 the possibility to explore various mapping of the application on the selected template architecture,
    40 and offers a high predictability of results with respect to cost and performance objectives.
    41 \\
    42 When this interactive, system level, design space exploration is completed (converging to
    43 a specific mapping on a specific version of the selected architectural template), the rest of the flow
    44 is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
    45 code for the software running on the embedded processors, and the bit-stream to program the target FPGA
    46 will be automatically generated by the COACH tools.
    47 %
    48 \parlf
    49 The strength of the COACH approach is the strong integration of the high-level synthesis tools
    50 in a platform based design flow supporting virtual prototyping and design space exploration.
    51 Most building blocks already exist (resulting from previous projects): the GAUT
    52 or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
    53 the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
    54 as well as the SoCLib library of SystemC simulation models.
    55 They must now be enhanced and integrated in a consistent design flow: this will
    56 be done in Magillem framework thanks to the IP-XACT standard.
    57 %The five academic laboratories worked very closely during more than one year (one monthly meeting
    58 %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
    59 %those various technologies, and to define the detailed architecture of the proposed design flow.
    60 %%%
     35%The proposed design flow starts from a high level description of the application, specified as a set of
     36%parallel tasks written in C, without any assumption on the hardware or software implementation
     37%of these tasks. It lets the system
     38%designer in charge of expressing the coarse grain parallelism of the application, gives the designer
     39%the possibility to explore various mapping of the application on the selected template architecture,
     40%and offers a high predictability of results with respect to cost and performance objectives.
     41%\\
     42%When this interactive, system level, design space exploration is completed (converging to
     43%a specific mapping on a specific version of the selected architectural template), the rest of the flow
     44%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
     45%code for the software running on the embedded processors, and the bit-stream to program the target FPGA
     46%will be automatically generated by the COACH tools.
     47%%
     48%\parlf
     49%The strength of the COACH approach is the strong integration of the high-level synthesis tools
     50%in a platform based design flow supporting virtual prototyping and design space exploration.
     51%Most building blocks already exist (resulting from previous projects): the GAUT
     52%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
     53%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
     54%as well as the SoCLib library of SystemC simulation models.
     55%They must now be enhanced and integrated in a consistent design flow: this will
     56%be done in Magillem framework thanks to the IP-XACT standard.
     57%%The five academic laboratories worked very closely during more than one year (one monthly meeting
     58%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
     59%%those various technologies, and to define the detailed architecture of the proposed design flow.
     60%%%%
    6161\parlf
    6262In HPC (High Performance Computing), the targeted application is an existing one
    … …  
    6969This will allow SMEs to enter HPC market for the applications that are
    7070unadapted to the current GPU based solutions.
     71\parlf
     72Coach generates SoC which is part of larger system. Thus it's important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC.
     73\begin{center}\begin{minipage}{.8\linewidth}\textit{
     74The third objective of COACH is to facilitate the integration of generated SoC in global system design flow.
     75}\end{minipage}\end{center}
    7176%%%
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