Changeset 297 for anr/section-2.tex

Timestamp:

Dec 16, 2010, 2:13:23 PM (14 years ago)

Author:

coach

Message:

 

File:

• anr/section-2.tex (modified) (5 diffs)

anr/section-2.tex

@@ -8 +8 @@
 software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
 Only very few SMEs have these multiple expertises and are present on the embedded system market.
+Furthermore, even small design services in the big companies are facing the same issue.
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
-The major objective of COACH is to provide to SMEs an open-source framework to design
-embedded systems on FPGA devices by system designers.
+The major objective of COACH is to provide to system designers, an affordable
+open-source framework to design embedded systems on FPGA devices.
 }\end{minipage}\end{center}
 %Current design methodologies provide quite low-level abstraction capabilities, and 
@@ -19 +20 @@
 %%%
 \parlf
-The COACH project will leverage on the expertise gained in the field of virtual prototyping
-with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
+The COACH project will propose a new design flow based on a small number of architectural templates.
 An architectural template is a generic, parameterized architecture, relying on a predefined library 
 of IP cores. 
@@ -42 +42 @@
 When this interactive, system level, design space exploration is completed (converging to
 a specific mapping on a specific version of the selected architectural template), the rest of the flow 
-is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary
-code for the software running on the embedded processors, and the bit-stream to program the the target FPGA 
+is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary
+code for the software running on the embedded processors, and the bit-stream to program the target FPGA 
 will be automatically generated by the COACH tools.
 %
@@ -50 +50 @@
 in a platform based design flow supporting virtual prototyping and design space exploration.
 Most building blocks already exist (resulting from previous projects): the GAUT 
-or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology,
-the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
-as well as the SoCLib library of systemC simulation models. They must now be enhanced and integrated in
-a consistent design flow.
+or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology,
+the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool,
+as well as the SoCLib library of SystemC simulation models.
+They must now be enhanced and integrated in a consistent design flow: this will
+be done in Magillem framework thanks to the IP-XACT standard.
 %The five academic laboratories worked very closely during more than one year (one monthly meeting
 %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
@@ -59 +60 @@
 %%%
 \parlf
-In HPC (High Performance Computing), the targeted application is an existing application
+In HPC (High Performance Computing), the targeted application is an existing one
 running on a PC.
 The COACH framework helps designer to accelerate it by migrating critical parts into a
 SoC embedded into an FPGA device plugged to the PC PCI/X bus.
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
-The second objective of COACH is to extend the framework to HPC.
+The second objective of COACH is to extend the framework for HPC applications.
 }\end{minipage}\end{center}
 This will allow SMEs to enter HPC market for the applications that are
 unadapted to the current GPU based solutions.
 %%%
-\parlf
-In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
-have been previously developed by academic laboratories.
-
-
-%Finally, the key points of the proposed design flow are :
-%\begin{itemize} 
-%\item
-%\textbf{System level exploration}: The application coarse grain parallelism 
-%is explicitely described as a Tasks and Communication Graph (TCG).
-%A template architecture is selected, and the performances are evaluated
-%on various variant of this architecture using the SoCLib virtual protyping
-%environment. This result in a specific hardware/software partitioning.  
-%This system level exploration is fully controlled by the system designer, and is driven 
-%by cost, throughput, latency and power consumption criteria. 
-%
-%\item
-%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
-%identified as mandatory, they will be generated by the high level synthesis (HLS) tools. 
-%The COACH framework will integrate various HLS tools, supporting the micro-architectural space
-%design exploration. Here again, the exploration criteria are cost, throughput, latency
-%and power consumption.
-%At this stage, preliminary source-level transformations and optimisations by front-end
-%tools will be required to improve the efficiency of the back-end HLS tools.
-%
-%\item
-%\textbf{Early performance evaluation}: For each point in the design space,
-%figures of merit must be available such as throughput, latency, power
-%consumption, area, memory allocation and data locality. They are evaluated
-%by reliable estimators obtained by running the actual multi-task software 
-%application on the virtual prototype.
-%
-%\item
-%\textbf{Independance from the Target FPGA}: The COACH description of the system 
-%(both hardware and software) should be independent of the FPGA family.  
-%Every point of the design space can be implemented on any FPGA component,
-%as long as it contains the hardware ressources required by the selected architectural template.
-%Basically, COACH will support both \altera and \xilinx FPGA families.
-%\end{itemize}
-%
-
-
-