Changeset 319 for anr/section-etat-de-art.tex

Timestamp:

Jan 20, 2011, 12:50:48 PM (13 years ago)

Author:

coach

Message:

template for Christophe CV, minor language modifications

anr/annexe-cv.tex
anr/section-consortium-people.tex
anr/section-objectif.tex
anr/section-1.tex
anr/section-2.tex
anr/section-position.tex
anr/section-etat-de-art.tex
anr/section-issues.tex

File:

• anr/section-etat-de-art.tex (modified) (5 diffs)

anr/section-etat-de-art.tex

@@ -78 +78 @@
 \\
 In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx 
-Platform Studio XPS from \xilinx allows to describe a system, to synthesis it, 
+Platform Studio XPS from \xilinx allows to describe a system, to synthesize it, 
 to program it into a target FPGA and to upload a software application.
 Both SOPC Builder and XPS, allow designers to select and parameterize components from 
@@ -128 +128 @@
 \item The parallelism is extracted from initial specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
-must re-write the algorithmic specification while there is techniques such as polyedric
+must re-write the algorithmic specification while there are techniques such as polyedric
 transformations to increase the intrinsic parallelism,
 \item While they support limited loop transformations like loop unrolling and loop
-pipelining, current HLS tools do not provide support for design space exploration neither
-through automatic loop transformations nor through memory mapping,
+pipelining, current HLS tools do not provide support for design space exploration, either
+through automatic loop transformations or through memory mapping,
 \item Despite having the same input language (C/C++), they are sensitive to the style in
-which the algorithm dis written. Consequently, engineering work is required to swap from 
+which the algorithm is written. Consequently, engineering work is required to swap from 
 a tool to another,
 \item They do not respect accurately the frequency constraint when they target an FPGA device.
@@ -146 +146 @@
 \label{soa:asip}
 ASIP (Application-Specific Instruction-Set Processor) are programmable
-processors in which both the instruction and the micro architecture have
+processors in which both the instruction set and the micro architecture have
 been tailored to a given application domain or to a
 specific application.  This specialization usually offers a good compromise
@@ -220 +220 @@
 tool for many other optimization, like memory reduction and locality
 improvement. Another point is
-that the polyhedral domain \emph{stricto sensu} applies only to
+that the polyhedral model \emph{stricto sensu} applies only to
 very regular programs. Its extension to more general programs is
 an active research subject.
@@ -245 +245 @@
 are members of the consortium and the board is incorporating top actors 
 (STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the 
-wide adoption by industry. Initiatives have already work for extending this standard
+wide adoption by industry. Initiatives have already% work for (paul)
+attempted to extend this standard
 to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent 
 Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for