Changeset 339 for anr/section-etat-de-art.tex

Timestamp:

Jan 31, 2011, 3:32:59 PM (13 years ago)

Author:

coach

Message:

corrections de langage

File:

• anr/section-etat-de-art.tex (modified) (6 diffs)

anr/section-etat-de-art.tex

@@ -44 +44 @@
 researches on HPC-FPGA are mainly conducted in the USA. 
 None of the approaches developed in these researches are fulfilling entirely the
-challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator,
+challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator,
 but extension generation is not automated and requires hardware design skills.
 Mitrionics has an elegant solution based on a compute engine specifically
@@ -74 +74 @@
 tool will then automatically generate synthesizable Hardware Description
 Language (HDL) code mapped to \xilinx pre-optimized algorithms.
-However, this tool targets only DSP based algorithms, \xilinx FPGAs and
+However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and
 cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
 \\
 In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx 
-Platform Studio XPS from \xilinx allows to describe a system, to synthesize it, 
+Platform Studio XPS from \xilinx allow to describe a system, to synthesize it, 
 to program it into a target FPGA and to upload a software application.
 Both SOPC Builder and XPS, allow designers to select and parameterize components from 
@@ -126 +126 @@
 Low power consumption constraint which is mandatory for embedded systems is not yet 
 well handled or not handled at all by the HLS tools already available,
-\item The parallelism is extracted from initial specification.
+\item The parallelism is extracted from the initial specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
 must re-write the algorithmic specification while there are techniques such as polyedric
@@ -166 +166 @@
 This approach however has a severe weakness, since it also significantly reduces 
 opportunities for achieving good speedups (most speedups remain between 1.5x and 
-2.5x), since ISEs performance is generally tied down by I/O constraints as 
+2.5x), since ISEs performance is generally limited by I/O constraints as 
 they generally rely on the main CPU register file to access data.
 
@@ -219 +219 @@
 As a side effect, it has been observed that the polyhedral model is a useful
 tool for many other optimization, like memory reduction and locality
-improvement. Another point is
+improvement. Itshould be noted 
 that the polyhedral model \emph{stricto sensu} applies only to
 very regular programs. Its extension to more general programs is
@@ -245 +245 @@
 are members of the consortium and the board is incorporating top actors 
 (STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the 
-wide adoption by industry. Initiatives have already% work for (paul)
+wide adoption by industry. Initiatives have already
 attempted to extend this standard
-to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent 
+to the AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent 
 Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for 
 further releases.