Changeset 335 for anr


Ignore:
Timestamp:
Jan 28, 2011, 5:22:40 PM (14 years ago)
Author:
coach
Message:

Mise à jour INRIA Rennes - 28 janv

Location:
anr
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • anr/annexe-cv.tex

    r331 r335  
    126126    \end{itemize}
    127127\end{cvenv}
     128%
     129\begin{cvenv}
     130  {{Charot}{François}{52}}
     131  {INRIA researcher }
     132  {PhD (1982)}
     133  {{60}{\cite{Martin09c} \cite{Martin09d} \cite{Wolinski09a} \cite{RAFFIN:2010:INRIA-00539874:1}}}
     134  \item[Course of Lectures]\mbox{}
     135       embedded system design
     136 \item[Projects]\mbox{}
     137    \begin{itemize}
     138       \item SocLib and ROMA ANR projects
     139       \item Nano2012 RecMotifs project
     140   \end{itemize}
     141\end{cvenv}

  • anr/anr.bib

    r331 r335  
    914914  year =         {2009}
    915915}
     916
     917
     918%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     919%%% FC
     920
     921@InProceedings{    Martin09c,
     922 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
     923 title          = {Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system},
     924 address       = {Boston, MA, USA},
     925month         = jul,
     926 year           = 2009,
     927booktitle ={Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors},
     928pages = {145-152},
     929publisher = {IEEE Computer Society},
     930        x-proceedings = {yes},
     931        x-international-audience = {yes},
     932        x-editorial-board = {yes},
     933        x-invited-conference = {no},
     934        x-hal = {no}
     935}
     936
     937@InProceedings{Martin09d,
     938 author        = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.},
     939 title          = {Constraint-Driven Identification of Application Specific Instructions in the DURASE system},
     940 booktitle     = {Proc. of Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
     941 address = {Samos, Greece},
     942month         = jul,
     943 year           = 2009,
     944volume = {5657},
     945series = {Lecture Notes in Computer Science},
     946pages = {194-203},
     947publisher = {Springer},
     948        x-proceedings = {yes},
     949        x-international-audience = {yes},
     950        x-editorial-board = {yes},
     951        x-invited-conference = {no},
     952        x-hal = {no}
     953}
     954@InProceedings{    Wolinski09a,
     955 author        = {Wolinski, Ch. and Kuchcinski, K. and Raffin, E. and Charot, F.},
     956 title          = {Architecture-Driven Synthesis of Reconfigurable Cells},
     957booktitle = {{Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)}},
     958 address       = {Patras, Greece},
     959month         = sep,
     960 year           = 2009,
     961pages = {531 - 538 },
     962doi={10.1109/DSD.2009.183},
     963        x-proceedings = {yes},
     964        x-international-audience = {yes},
     965        x-editorial-board = {yes},
     966        x-invited-conference = {no},
     967        x-hal = {no}
     968}
     969@inproceedings{RAFFIN:2010:INRIA-00539874:1,
     970    HAL_ID = {inria-00539874},
     971    URL = {http://hal.inria.fr/inria-00539874/en/},
     972    title = { {S}cheduling, {B}inding and {R}outing {S}ystem for a {R}un-{T}ime {R}econfigurable {O}perator {B}ased {M}ultimedia {A}rchitecture},
     973    author = {{R}affin, {E}rwan and {W}olinski, {C}hristophe and {C}harot, {F}ran{\c{c}}ois and {K}uchcinski, {K}rzysztof and {G}uyetant, {S}t{\'e}phane and {C}hevobbe, {S}t{\'e}phane and {C}asseau, {E}mmanuel},
     974    booktitle = {Conference on {D}esign and {A}rchitectures for {S}ignal and {I}mage {P}rocessing ({DASIP} 2010)},
     975    address = {{E}dinburgh {R}oyaume-{U}ni },
     976    audience = {internationale },
     977    month = oct,
     978    year = {2010},
     979    URL = {http://hal.inria.fr/inria-00539874/PDF/dasip2010.pdf},
     980    x-hal={inria-00539874},
     981}

  • anr/anr.sty

    r305 r335  
    8888    \let\xcoach\relax%
    8989    \let\xcoachplus\relax%
    90     \let\irisa\relax    \let\Sirisa\relax%
     90    \let\inria\relax    \let\Sinria\relax%
    9191    \let\lip\relax      \let\Slip\relax%
    9292    \let\tima\relax     \let\Stima\relax%
    … …  
    107107{%
    108108\let\ALL\disable%
    109 \let\IRISA\disable%
     109\let\INRIA\disable%
    110110\let\LIP\disable%
    111111\let\TIMA\disable%
    … …  
    117117}{%
    118118\ifx\ALL\enable%
    119   \ifx\IRISA\disable\let\IRISA\enable\fi%
     119  \ifx\INRIA\disable\let\INRIA\enable\fi%
    120120  \ifx\LIP\disable\let\LIP\enable\fi%
    121121  \ifx\UPMC\disable\let\UPMC\enable\fi%
    … …  
    128128\def\@leader{\begin{small}\textcolor{red}{lead.}\end{small}}
    129129\def\@partner{\begin{small}\textcolor{blue}{part.}\end{small}}
    130 \def\@IRISA{\ifx\IRISA\disable{}\else\ifx\IRISA\enable{\@partner}\else{\@leader}\fi\fi}%
     130\def\@INRIA{\ifx\INRIA\disable{}\else\ifx\INRIA\enable{\@partner}\else{\@leader}\fi\fi}%
    131131\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{\@partner}\else{\@leader}\fi\fi}%
    132132\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{\@partner}\else{\@leader}\fi\fi}%
    … …  
    137137\def\@MDS{\ifx\MDS\disable{}\else\ifx\MDS\enable{\@partner}\else{\@leader}\fi\fi}%
    138138\begin{tabular}{|c|c|c|c|c|c|c|c|}\hline
    139 \Sirisa  & \Slip  & \Stima  & \Subs  & \Supmc  & \Smds & \Sbull  & \Sthales \\\hline
    140 \@IRISA  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@MDS & \@BULL  & \@THALES \\\hline
     139\Sinria  & \Slip  & \Stima  & \Subs  & \Supmc  & \Smds & \Sbull  & \Sthales \\\hline
     140\@INRIA  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@MDS & \@BULL  & \@THALES \\\hline
    141141\end{tabular}\par
    142142}
    … …  
    291291\let\xcoach\relax%
    292292\let\xcoachplus\relax%
    293 \let\irisa\relax\let\Sirisa\relax%
     293\let\inria\relax\let\Sinria\relax%
    294294\let\lip\relax\let\Slip\relax%
    295295\let\tima\relax\let\Stima\relax%

  • anr/anr.tex

    r333 r335  
    7272\def\Sformat#1{\begin{small}\textsc{#1}\end{small}}
    7373\def\inria{INRIA\xspace}          \def\Sinria{\Sformat{INRIA}\xspace}
    74 \def\irisa{INRIA/\-CAIRN\xspace}    \def\Sirisa{\Sformat{INRI}\xspace}
     74%\def\irisa{INRIA/\-CAIRN\xspace}    \def\Sirisa{\Sformat{INRI}\xspace}
    7575\def\lip{ENS Lyon/LIP/Compsys\xspace}     \def\Slip{\Sformat{LIP}\xspace}
    7676\def\tima{TIMA\xspace}            \def\Stima{\Sformat{TIMA}\xspace}
    … …  
    8585\def\xilinx{XILINX\xspace}        \def\Sxilinx{\Sformat{XILX}\xspace}
    8686
    87 \def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
     87\def\alllabs{\inria \citi \lip \tima \ubs \upmc}
    8888\def\allcompagnies{\bull \thales \mds\xspace}
    8989
    … …  
    218218\begin{description}
    219219  \item[partner]
    220     \Sirisa for \irisa, \Slip for \lip, \Stima for \tima, \Subs for \ubs,
     220    \Sinria for \inria, \Slip for \lip, \Stima for \tima, \Subs for \ubs,
    221221    \Supmc for \upmc, \Sxilinx for \xilinx, \Sbull for \bull, \Sthales for \thales,
    222222    and \Smds for \mds.

  • anr/gantt.l

    r303 r335  
    5353struct partner_def { char *key, *name, *fnfull, *fnshort; } partner_table[] = {
    5454    { "UNKNOW" ,"relax"  ,0                             ,0                        },
    55     { "irisa"  ,"irisa"  ,"table_inria_cairn_full.tex"  ,"table_inria_cairn_short.tex"  },
     55    { "inria"  ,"inria"  ,"table_inria_cairn_full.tex"  ,"table_inria_cairn_short.tex"  },
    5656    { "lip"    ,"lip"    ,"table_inria_compsys_full.tex","table_inria_compsys_short.tex"    },
    5757    { "tima"   ,"tima"   ,"table_tima_full.tex"         ,"table_tima_short.tex"   },

  • anr/section-1.tex

    r319 r335  
    109109Operating system and communication middleware (\tima, \upmc),
    110110MPSoC architectures (\tima, \ubs, \upmc),
    111 ASIP architectures (\irisa),
     111ASIP architectures (\inria),
    112112High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip),
    113113HPC (\bull, \thales), tools integration in IP-XACT flow (\mds).
    … …  
    118118on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS),
    119119on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
    120 on the ROMA~\cite{roma} project for ASIP,
     120on the ROMA~\cite{roma, RAFFIN:2010:INRIA-00539874:1} project for ASIP,
    121121on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and
    122122transformations,

  • anr/section-consortium-desc.tex

    r333 r335  
    1515- TIMA: Architecture, virtual prototyping, HLS
    1616- LAB-STICC: HLS, compilation
    17 - INRIA/CAIRN: XXX
     17- INRIA: ASIP design
    1818
    1919- Magillem: IP-XACT and industrial flow integration
    … …  
    2525
    2626%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    27 \subsubsection{\inria/CAIRN}
     27\subsubsection{\inria}
    2828
    2929INRIA, the French national institute for research in computer science

  • anr/section-consortium-people.tex

    r333 r335  
    3939contributor & Olivier     & Garry       & R\&D Engineer       & SW development & 9 & Tools and demonstrator implementation \\\hline
    4040
    41 \peopletabularentry{\irisa}
    42 ...         & Derien      & Steven      & ...                 & ...         & ... & ... \irisa \\\hline
    43 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
     41\peopletabularentry{\inria}
     42responsible        & Charot      & François      & INRIA researcher&SOC ASIP         & 12 & expertise in architecture, microarchitecture, SoC design. Participation to Task-1/2/4/8  \\\hline
     43contributor         & Derrien      & Steven      & Associate professor&
     44HLS compilation          & 12& expertise in architecture, microarchitecture, SoC design \\\hline
    4445
    4546\peopletabularentry{\lip}

  • anr/section-position.tex

    r319 r335  
    6464    It provides also embedded operating systems and software/hardware
    6565    communication middleware.
    66   \item[ROMA] The ROMA ANR project \cite{roma}
     66  \item[ROMA] The ROMA ANR project (2007-2010) \cite{roma,RAFFIN:2010:INRIA-00539874:1}
    6767    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
    6868    proposes to develop a reconfigurable processor, exhibiting high

  • anr/section-project-description.tex

    r310 r335  
    3838(one for synthesis, one for simulation).
    3939For generating the coprocessor of a task mapped as hardware, \verb+CSG+
    40 controls the HAS tools described below.
     40controls the \verb!HAS! (Hardware Accelerator Synthesis) tools described below.
    4141From these inputs \verb!CSG! can generate the entire system (both software and
    4242hardware) either as an IP under IP-XACT to integrate the SoC in larger
    … …  
    5252 architecture or the enhancement of existing template with IP.
    5353\parlf
    54 The software architecture for HAS is presented in figure~\ref{archi-hls}.
    55 The input is a single task of the process network. The HAS tools do not work
     54The software architecture for \verb!HAS! is presented in figure~\ref{archi-hls}.
     55The input is a single task of the process network. The \verb!HAS! tools do not work
    5656directly on the C++ task description but on an internal format called
    5757\xcoach generated by a plugin into the GNU C compiler (GCC).
    … …  
    8787        the architectural templates and the design flow.
    8888\item[Task-3: \textit{System generation}] This task addresses the prototyping and
    89     the generation of digital system. Apart from HAS that belongs to task 3
     89    the generation of digital system. Apart from \verb!HAS! that belongs to task 3
    9090    and 4, its components are those presented figure~\ref{archi-csg}
    9191    (e.g.  \verb!CSG!, operating systems).

  • anr/section-ressources.tex

    r332 r335  
    3636
    3737%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    38 \subsection{Partner 1: \irisa}
     38\subsection{Partner 1: \inria}
    3939
    4040\begin{description}
    … …  
    274274\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}}
    275275\begin{minipage}[b]{.47\linewidth}\center
    276 \input{table_inria_cairn_full.tex}\vspace{.5ex}\\  \irisa  \vspace{2.5ex}\\
     276\input{table_inria_cairn_full.tex}\vspace{.5ex}\\  \inria  \vspace{2.5ex}\\
    277277\input{table_mds_full.tex}\vspace{.5ex}\\       \mds \\
    278278\end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center

  • anr/task-backbone.tex

    r332 r335  
    5050        with the feed-backs of the demonstrator \STs.
    5151        \OtherPartner{0}{12}{\Slip}   {1:0:0}
    52         \OtherPartner{0}{12}{\Sirisa} {1:0:0}
     52        \OtherPartner{0}{12}{\Sinria} {1:0:0}
    5353        \OtherPartner{0}{12}{\Stima}  {2:0:0}
    5454        \OtherPartner{0}{12}{\Subs}   {2:0:0}
    … …  
    8181    \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{4:2:0}
    8282        \OtherPartner{0}{18}{\Supmc}  {.5:.5:0}
    83         \OtherPartner{0}{18}{\Stima}  {.5:.5:0}
     83        \OtherPartner{0}{18}{\Stima}  {.5:.5:0} 
     84        \OtherPartner{0}{18}{\Sinria}  {.5:.5:0}
    8485        \setMacroInAuxFile{specXcoachDoc}
    8586        Last release of XML specification of the \xcoach format enhanced with

  • anr/task-dissemination.tex

    r316 r335  
    6969    \itemL{21}{27}{d}{\Slip}{HAS front-end user manual}{0:.5:1}
    7070        This user manual shows how to apply loop transformations to a task.
    71     \itemL{21}{27}{d}{\Sirisa}{ASIP user manual}{0:1:1}
     71    \itemL{21}{27}{d}{\Sinria}{ASIP user manual}{0:1:1}
    7272        This user manual shows how to customize a processor to obtain an ASIP.
    7373    \itemL{21}{27}{d}{\Subs}{HLS user manual}{0:.5:1}
    … …  
    8181   \begin{livrable}
    8282   \itemL{12}{36}{d}{\Smds}{Publication, communication}{0:2:3}
    83         \OtherPartner{12}{36}{\Sirisa} {0:1:1}
     83        \OtherPartner{12}{36}{\Sinria} {0:1:1}
    8484        \OtherPartner{12}{36}{\Slip}   {0:1:1}
    8585        \OtherPartner{12}{36}{\Stima}  {0:1:1}

  • anr/task-frontend.tex

    r334 r335  
    11\begin{taskinfo}
    22\let\LIP\leader
    3 \let\IRISA\enable
     3\let\INRIA\enable
    44\let\UBS\enable
    55\let\UPMC\enable
    … …  
    2727  instructions definitions along with their occurrence in the application.
    2828    \begin{livrable}
    29       \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow}
     29      \itemV{0}{12}{x}{\Sinria}{ASIP compilation flow}
    3030        In this first version of the software, the computations patterns corresponding to
    3131        custom instructions are specified by the user, and then automatically extracted (when
    3232        beneficial) from the application intermediate representation.
    33       \itemL{18}{27}{x}{\Sirisa}{ASIP compilation flow}{0:6:3}
     33      \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{4:4:3}
    3434        In this second version, the software will also be able to automatically identify
    3535        interesting pattern candidates in the application code, and use them as custom
    … …  
    4343 of the architecture, along with its architectural extensions
    4444    \begin{livrable}
    45       \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS }
     45      \itemV{0}{12}{x}{\Sinria}{SystemC for extensible MIPS }
    4646      { A SystemC simulation model for a simple extensible MIPS architectural template }
    47       \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
     47      \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3:3:0}
    4848      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
    4949      its instruction set extensions}
    50       \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
     50      \itemV{3}{18}{h}{\Sinria}{VHDL for an extensible MIPS}
    5151      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
    52       \itemL{18}{27}{h}{\Sirisa}{VHDL for extensible MIPS}{9:9:3}
     52      \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{6:6.5:3}
    5353      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
    5454      its instruction set extensions}
    55       \itemL{27}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
     55      \itemL{27}{36}{d}{\Sinria}{Evaluation report }{0:0:2}
    5656      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
    5757      the different approaches}

  • anr/task-management.tex

    r304 r335  
    3333        \OtherPartner{0}{36}{\Stima}  {.5:.5:.5}%
    3434        \OtherPartner{0}{36}{\Slip}   {.5:.5:.5}%
    35         \OtherPartner{0}{36}{\Sirisa} {.5:.5:.5}%
     35        \OtherPartner{0}{36}{\Sinria} {.5:.5:.5}%
    3636        \OtherPartner{0}{36}{\Sthales}{.5:.5:.5}%
    3737        \OtherPartner{0}{36}{\Sbull}  {.5:.5:.5}%
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