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Changeset 339
- Timestamp:
- Jan 31, 2011, 3:32:59 PM (13 years ago)
- Location:
- anr
- Files:
-
- 3 edited
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section-etat-de-art.tex (modified) (6 diffs)
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section-issues.tex (modified) (5 diffs)
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section-position.tex (modified) (4 diffs)
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anr/section-etat-de-art.tex
r319 r339 44 44 researches on HPC-FPGA are mainly conducted in the USA. 45 45 None of the approaches developed in these researches are fulfilling entirely the 46 challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator,46 challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator, 47 47 but extension generation is not automated and requires hardware design skills. 48 48 Mitrionics has an elegant solution based on a compute engine specifically … … 74 74 tool will then automatically generate synthesizable Hardware Description 75 75 Language (HDL) code mapped to \xilinx pre-optimized algorithms. 76 However, this tool targets only DSP basedalgorithms, \xilinx FPGAs and76 However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and 77 77 cannot handle a complete SoC. Thus, it is not really a system synthesis tool. 78 78 \\ 79 79 In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx 80 Platform Studio XPS from \xilinx allow sto describe a system, to synthesize it,80 Platform Studio XPS from \xilinx allow to describe a system, to synthesize it, 81 81 to program it into a target FPGA and to upload a software application. 82 82 Both SOPC Builder and XPS, allow designers to select and parameterize components from … … 126 126 Low power consumption constraint which is mandatory for embedded systems is not yet 127 127 well handled or not handled at all by the HLS tools already available, 128 \item The parallelism is extracted from initial specification.128 \item The parallelism is extracted from the initial specification. 129 129 To get more parallelism or to reduce the amount of required memory in the SoC, the user 130 130 must re-write the algorithmic specification while there are techniques such as polyedric … … 166 166 This approach however has a severe weakness, since it also significantly reduces 167 167 opportunities for achieving good speedups (most speedups remain between 1.5x and 168 2.5x), since ISEs performance is generally tied downby I/O constraints as168 2.5x), since ISEs performance is generally limited by I/O constraints as 169 169 they generally rely on the main CPU register file to access data. 170 170 … … 219 219 As a side effect, it has been observed that the polyhedral model is a useful 220 220 tool for many other optimization, like memory reduction and locality 221 improvement. Another point is221 improvement. Itshould be noted 222 222 that the polyhedral model \emph{stricto sensu} applies only to 223 223 very regular programs. Its extension to more general programs is … … 245 245 are members of the consortium and the board is incorporating top actors 246 246 (STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the 247 wide adoption by industry. Initiatives have already % work for (paul)247 wide adoption by industry. Initiatives have already 248 248 attempted to extend this standard 249 to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent249 to the AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent 250 250 Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for 251 251 further releases. -
anr/section-issues.tex
r319 r339 27 27 \end{table} 28 28 % 29 Microelectronic components allow theintegration of complex functions into products, increases29 Microelectronic components allow integration of complex functions into products, increases 30 30 commercial attractivity of these products and improves their competitivity. 31 \cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 minimum.31 \cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 at least. 32 32 Multimedia and communication sectors have taken advantage from microelectronics facilities 33 33 thanks to the developpment of design methodologies and tools for embedded systems. … … 36 36 An IC foundry costs several billions of euros and the fabrication of a specific circuit 37 37 costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 38 million USD. Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium 39 volume markets and the new trend for building the new generation products will be multi processors SoCs and programmable logic for co-processsing. 38 million \$ . Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium 39 volume markets and the new trend for building the new generation products will be multi processors SoCs and 40 programmable logic for co-processsing. 40 41 \\ 41 According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), the global growth is 30 Billons\$ between 2009-2013 for multimedia and communication sectors; this is 6 times more than all other domains like security, home automation, health. 42 The predominance%paul 43 the multimedia and communication sectors 44 %results paul 45 are due to their being predominently a mass market. 42 According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), 43 the global growth is 30 billon\$ between 2009-2013 for the multimedia and communication sectors; this is 44 6 times more than all other domains like security, home automation or health. 45 The predominance of the multimedia and communication sectors are due to their being predominently a mass market. 46 46 % 47 47 \subsubsection*{FPGAs and Embedded Systems} … … 82 82 Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic 83 83 products (eg. PDAs and nomad items) and even personal computers. 84 To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools. 84 To take benefit of such architectures, developping and deploying application will require innovative 85 codesign methods and tools. 85 86 86 87 % … … 96 97 The COACH project proposes an open-source framework for mapping multi-tasks software applications 97 98 on Field Programmable Gate Array circuits (FPGA). 98 It aims to propose solutions to the societal/economical challenges by99 Its aim is to propose solutions to the societal/economical challenges by 99 100 providing SMEs novel design capabilities enabling them to increase their 100 101 design productivity with design exploration and synthesis methods that are placed on top … … 109 110 to launch start-ups in software engineering. 110 111 \\ 111 So this may increase the total%amount (paul) 112 number of engineers working in this domain: today in France the total is only 26,000 of which 16,000 are in big companies \cite{rapport-ministere}. 112 So this may increase the total 113 number of engineers working in this domain: today in France the total is only 26,000 of which 114 16,000 are in big companies \cite{rapport-ministere}. -
anr/section-position.tex
r335 r339 40 40 design flow, using the IP-XACT IEEE 1685 standard 41 41 \end{itemize} 42 COACH outcomewill contribute to strengthen Europe's competitive position by developing42 The COACH results will contribute to strengthen Europe's competitive position by developing 43 43 technologies and methodologies for product design, focusing (in compliance with the 44 44 %scope of the above program) on technologies, engineering methodologies, novel tools, … … 68 68 proposes to develop a reconfigurable processor, exhibiting high 69 69 silicon density and power efficiency, able to adapt its computing 70 structure to computation patterns that can be speed-up and/or70 structure to computation patterns that can be faster or more 71 71 power efficient. %The ROMA project study a pipeline of 72 72 %evolved low-power coarse grain reconfigurable operators to avoid … … 152 152 \subsubsection*{Relevance to the call axis} 153 153 This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing 154 methods and tools for the design of application to be run on platforms of the next generation. Results will be gained in term of productivity, 154 methods and tools for the design of application to be run on platforms of the next generation. 155 Inprovements can be expected for productivity, 155 156 time-to-market (automation and code generation) and safety (management of high level sepcifications down to implementation). 156 157 In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES, … … 182 183 % 183 184 The results of the COACH project will help users to build cryptographic secure systems implemented in 184 hardware or both in software/hardware in an effective way, substantially enhancing the185 pro cess productivity of the cryptographic algorithms hardware synthesis, improving the185 in a combination of hardware and software in an effective way, substantially enhancing the 186 productivity of the field, improving the 186 187 quality and reducing the design time and the cost of synthesised cryptographic devices. 187 188 %
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