- Timestamp:
- Jan 31, 2011, 3:39:10 PM (14 years ago)
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anr/section-objectif.tex
r319 r340 43 43 Furthermore in the HPC case, an executable containing the host application is 44 44 also generated and the user will be able to launch the application by loading 45 the bitstream on an FPGA and running the executable on PC.45 the bitstream on an FPGA and running the executable on a PC. 46 46 \end{description} 47 47 … … 64 64 \item[\textit{Design Space Exploration by Virtual Prototyping}]: 65 65 The COACH environment will allow to easily map a parallel application (formally described as 66 an abstract network of process and communication channels) 66 an abstract network of process and communication channels). 67 67 COACH will permit the system designer to explore the design space, and to define the best 68 68 hardware/software partitioning of the application. … … 74 74 and the HLS tools of COACH will support a common language and coding style 75 75 to avoid re-engineering by the designer. 76 COACH will provide a tool which will automatically explore the%paul 77 coprocessor micro-architectural design space. 76 COACH will provide a tool which will automatically explore the coprocessor micro-architectural design space. 78 77 \item[\textit{High-level code transformation}]: 79 78 COACH will allow to optimize the memory usage, to enhance the parallelism through … … 87 86 COACH will support code transformation by providing a source to source C2C tool. 88 87 \item[\textit{Unified Hardware/Software communication middleware}]: 89 COACH will rely on he SoCLib experience to implement an unified hardware/software communication88 COACH will rely on the SoCLib experience to implement an unified hardware/software communication 90 89 infrastructure and communication APIs (Application Programming Interface), to support 91 90 communications between software tasks running on embedded processors and dedicated
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