Changeset 339 for anr


Ignore:
Timestamp:
Jan 31, 2011, 3:32:59 PM (14 years ago)
Author:
coach
Message:

corrections de langage

Location:
anr
Files:
3 edited

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  • anr/section-etat-de-art.tex

    r319 r339  
    4444researches on HPC-FPGA are mainly conducted in the USA.
    4545None of the approaches developed in these researches are fulfilling entirely the
    46 challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator,
     46challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator,
    4747but extension generation is not automated and requires hardware design skills.
    4848Mitrionics has an elegant solution based on a compute engine specifically
    … …  
    7474tool will then automatically generate synthesizable Hardware Description
    7575Language (HDL) code mapped to \xilinx pre-optimized algorithms.
    76 However, this tool targets only DSP based algorithms, \xilinx FPGAs and
     76However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and
    7777cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
    7878\\
    7979In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx
    80 Platform Studio XPS from \xilinx allows to describe a system, to synthesize it,
     80Platform Studio XPS from \xilinx allow to describe a system, to synthesize it,
    8181to program it into a target FPGA and to upload a software application.
    8282Both SOPC Builder and XPS, allow designers to select and parameterize components from
    … …  
    126126Low power consumption constraint which is mandatory for embedded systems is not yet
    127127well handled or not handled at all by the HLS tools already available,
    128 \item The parallelism is extracted from initial specification.
     128\item The parallelism is extracted from the initial specification.
    129129To get more parallelism or to reduce the amount of required memory in the SoC, the user
    130130must re-write the algorithmic specification while there are techniques such as polyedric
    … …  
    166166This approach however has a severe weakness, since it also significantly reduces
    167167opportunities for achieving good speedups (most speedups remain between 1.5x and
    168 2.5x), since ISEs performance is generally tied down by I/O constraints as
     1682.5x), since ISEs performance is generally limited by I/O constraints as
    169169they generally rely on the main CPU register file to access data.
    170170
    … …  
    219219As a side effect, it has been observed that the polyhedral model is a useful
    220220tool for many other optimization, like memory reduction and locality
    221 improvement. Another point is
     221improvement. Itshould be noted
    222222that the polyhedral model \emph{stricto sensu} applies only to
    223223very regular programs. Its extension to more general programs is
    … …  
    245245are members of the consortium and the board is incorporating top actors
    246246(STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the
    247 wide adoption by industry. Initiatives have already% work for (paul)
     247wide adoption by industry. Initiatives have already
    248248attempted to extend this standard
    249 to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent
     249to the AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent
    250250Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for
    251251further releases.

  • anr/section-issues.tex

    r319 r339  
    2727\end{table}
    2828%
    29 Microelectronic components allow the integration of complex functions into products, increases
     29Microelectronic components allow integration of complex functions into products, increases
    3030commercial attractivity of these products and improves their competitivity.
    31 \cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 minimum.
     31\cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 at least.
    3232Multimedia and communication sectors have taken advantage from microelectronics facilities
    3333thanks to the developpment of design methodologies and tools for embedded systems.
    … …  
    3636An IC foundry costs several billions of euros and the fabrication of a specific circuit
    3737costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
    38 million USD. Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
    39 volume markets and the new trend for building the new generation products will be multi processors SoCs and programmable logic for co-processsing.
     38million \$ . Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
     39volume markets and the new trend for building the new generation products will be multi processors SoCs and
     40programmable logic for co-processsing.
    4041\\
    41 According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), the global growth is 30 Billons\$ between 2009-2013 for multimedia and communication sectors; this is 6 times more than all other domains like security, home automation, health.
    42 The predominance%paul
    43 the multimedia and communication sectors
    44 %results paul
    45 are due to their being predominently a mass market.
     42According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010),
     43the global growth is 30 billon\$ between 2009-2013 for the multimedia and communication sectors; this is
     446 times more than all other domains like security, home automation or health.
     45The predominance of the multimedia and communication sectors are due to their being predominently a mass market.
    4646%
    4747\subsubsection*{FPGAs and Embedded Systems}
    … …  
    8282Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic
    8383products (eg. PDAs and nomad items) and even personal computers.
    84 To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools.
     84To take benefit of such architectures, developping and deploying application will require innovative
     85codesign methods and tools.
    8586
    8687%
    … …  
    9697The COACH project proposes an open-source framework for mapping multi-tasks software applications
    9798on Field Programmable Gate Array circuits (FPGA).
    98 It aims to propose solutions to the societal/economical challenges by
     99Its aim is to propose solutions to the societal/economical challenges by
    99100providing SMEs novel design capabilities enabling them to increase their
    100101design productivity with design exploration and synthesis methods that are placed on top
    … …  
    109110to launch start-ups in software engineering.
    110111\\
    111 So this may increase the total%amount (paul)
    112 number of engineers working in this domain: today in France the total is only 26,000 of which 16,000 are in big companies \cite{rapport-ministere}.
     112So this may increase the total
     113number of engineers working in this domain: today in France the total is only 26,000 of which
     11416,000 are in big companies \cite{rapport-ministere}.

  • anr/section-position.tex

    r335 r339  
    4040design flow, using the IP-XACT IEEE 1685 standard
    4141\end{itemize}
    42 COACH outcome will contribute to strengthen Europe's competitive position by developing
     42The COACH results will contribute to strengthen Europe's competitive position by developing
    4343technologies and methodologies for product design, focusing (in compliance with the
    4444%scope of the above program) on technologies, engineering methodologies, novel tools,
    … …  
    6868    proposes to develop a reconfigurable processor, exhibiting high
    6969    silicon density and power efficiency, able to adapt its computing
    70     structure to computation patterns that can be speed-up and/or
     70    structure to computation patterns that can be faster or more
    7171    power efficient.  %The ROMA project study a pipeline of
    7272    %evolved low-power coarse grain reconfigurable operators to avoid
    … …  
    152152\subsubsection*{Relevance to the call axis}
    153153This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing
    154 methods and tools for the design of application to be run on platforms of the next generation. Results will be gained in term of productivity,
     154methods and tools for the design of application to be run on platforms of the next generation.
     155Inprovements can be expected for productivity,
    155156time-to-market (automation and code generation) and safety (management of high level sepcifications down to implementation).
    156157In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES,
    … …  
    182183%
    183184The results of the COACH project will help users to build cryptographic secure systems implemented in
    184 hardware or both in software/hardware in an effective way, substantially enhancing the
    185 process productivity of the cryptographic algorithms hardware synthesis, improving the
     185in a combination of hardware and software in an effective way, substantially enhancing the
     186productivity of the field, improving the
    186187quality and reducing the design time and the cost of synthesised cryptographic devices.
    187188%
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