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Timestamp:
Feb 1, 2011, 4:13:41 PM (14 years ago)
Author:
coach
Message:

minor language modifications

File:
1 edited

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  • anr/section-consortium-desc.tex

    r335 r348  
    1212for reaching the objectives (technical innovation and industrial evaluation for further exploitation).
    1313Each academic partner is expert in a specific area and each industrial brings a different approach to the use of the tools:
    14 - LIP6: MPSoC design and HLS
    15 - TIMA: Architecture, virtual prototyping, HLS
    16 - LAB-STICC: HLS, compilation
    17 - INRIA: ASIP design
    18 
    19 - Magillem: IP-XACT and industrial flow integration
    20 - BULL: HPC
    21 - THALES: XXX
     14\begin{itemize}
     15\item LIP6: MPSoC design and HLS
     16\item TIMA: Architecture, virtual prototyping, HLS
     17\item LAB-STICC: HLS, compilation
     18\item INRIA: ASIP design
     19\item LIP: compilation, polyhedral model, HPC
     20\item Magillem: IP-XACT and industrial flow integration
     21\item BULL: HPC
     22\item THALES: XXX
     23\end{itemize}
    2224
    2325Thales will represent the FPGA users, BULL the HPC users, and Magillem the SoC integrators.
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