Changeset 35


Ignore:
Timestamp:
Jan 15, 2010, 2:33:20 PM (15 years ago)
Author:
coach
Message:
 
Location:
anr
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • anr/anr.sty

    r27 r35  
    44
    55%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     6\newwrite\ganttdata
     7\immediate\openout\ganttdata=anr.gantt
     8
    69\def\enable{enable}
    710\def\disable{disable}
    … …  
    6063
    6164%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     65\newcount\taskcnt\taskcnt=-1
     66\newcount\subtaskcnt
     67\newcount\livrablecnt
    6268\newenvironment{workpackage}[1]%
    63 {\newcount\wpcnt\wpcnt=0%
    64  \def\taskname{#1}%
     69{\global\advance\taskcnt1
     70 \global\subtaskcnt0
     71 \def\taskname{T\the\taskcnt}%
    6572 \begin{description}%
    6673 \let\itemsave\item%
    6774 \def\item{%
    68     \advance\wpcnt1
    69     \def\wpname{\taskname-\the\wpcnt}%
    70     \itemsave[\wpname]}}
     75    \global\advance\subtaskcnt1
     76    \def\subtaskname{S\taskname-\the\subtaskcnt}%
     77    \itemsave[\subtaskname]}}
    7178{\end{description}}
    7279
    … …  
    7481\newenvironment{livrable}%
    7582{%
     83 \livrablecnt-1
    7684 \ifvmode\else\\\fi
    7785 \def\item##1##2##3##4##5##6{%
    78     \gdef\name{\wpname##1}%
     86        \def\tmpa{##1}\def\vers{}
     87        \def\tmp{}  \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{VF}\fi%
     88    \def\tmp{1} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi%
     89    \def\tmp{V1}\ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi%
     90    \def\tmp{2} \ifx\tmp\tmpa\def\vers{V2}\fi%
     91    \def\tmp{V2}\ifx\tmp\tmpa\def\vers{V2}\fi%
     92    \def\tmp{3} \ifx\tmp\tmpa\def\vers{V3}\fi%
     93    \def\tmp{V3}\ifx\tmp\tmpa\def\vers{V3}\fi%
     94    \def\tmp{F} \ifx\tmp\tmpa\def\vers{VF}\fi%
     95    \def\tmp{VF}\ifx\tmp\tmpa\def\vers{VF}\fi%
     96    %\gdef\name{D-\the\taskcnt\the\subtaskcnt\the\livrablecnt-##1}%
     97    \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}%
     98    {
     99      \let\xcoach\relax
     100      \let\xilinx\relax
     101      \let\altera\relax
     102      \immediate\write\ganttdata{%
     103        T=\the\taskcnt\space S=\the\subtaskcnt\space%
     104        DV=\the\livrablecnt\space BM=##2 EM=##3 TITLE=##6%
     105      }
     106    }
    79107    \\\hline
    80108    \begin{small}\textsc{\name}\end{small} &

  • anr/task-0.tex

    r28 r35  
    2323    patners to sign it.
    2424    \begin{livrable}
    25     \item{-VF}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by
     25    \item{}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by
    2626        all the partners.
    2727    \end{livrable}
    2828\item This \ST consists of the managment of deliverables.
    2929    \begin{livrable}
    30     \item{-1-VF}{0}{12}{d}{\Supmc}{First progress report}
    31     \item{-2-VF}{12}{24}{d}{\Supmc}{Second progress report}
    32     \item{-3-VF}{24}{36}{d}{\Supmc}{Final report}
     30    \item{}{0}{12}{d}{\Supmc}{First progress report}
     31    \item{}{12}{24}{d}{\Supmc}{Second progress report}
     32    \item{}{24}{36}{d}{\Supmc}{Final report}
    3333    \end{livrable}
    3434\item This \ST consists of the set up of the web site and iof its managment.
    3535    \begin{livrable}
    36     \item{-VF}{0}{6}{}{\Supmc}{Web site setting}
     36    \item{}{0}{6}{}{\Supmc}{Web site setting}
    3737    \end{livrable}
    3838\end{workpackage}

  • anr/task-1.tex

    r28 r35  
    1818    MPSoC and its 3 targets hardware mapping).
    1919    \begin{livrable}
    20     \item{-1-V1}{0}{6}{d}{\Supmc}{user manual}
     20    \item{V1}{0}{6}{d}{\Supmc}{user manual}
    2121        The first milestone of the document for allowing demonstration
    2222        \ST to start.
    23     \item{-1-V1}{6}{18}{d}{\Supmc}{user manual}
     23    \item{V2}{6}{18}{d}{\Supmc}{user manual}
    2424        The second milestone takes into account the missing features
    2525        the demonstrators rise.
    26     \item{-1-VF}{18}{30}{d}{\Supmc}{user manual}
     26    \item{VF}{18}{30}{d}{\Supmc}{user manual}
    2727        Final release.
    2828    \end{livrable}
    … …  
    3535\item This \ST specifies the \xcoach format.
    3636    \begin{livrable}
    37     \item{-1-V1}{0}{6}{d x}{\Slip}{specification of \xcoach format}
     37    \item{V1}{0}{6}{d x}{\Slip}{specification of \xcoach format}
    3838        First release of the XML specification of the \xcoach format
    3939        and its associated documentation allowing to start HLS tools development.
    40     \item{-1-V2}{6}{12}{d x}{\Slip}{specification of \xcoach format}
     40    \item{V2}{6}{12}{d x}{\Slip}{specification of \xcoach format}
    4141        Second release of XML specification of the \xcoach format
    4242        taking into account the corrections and modifications that the
    4343        developers of HLS tools rise.
    44     \item{-1-VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format}
     44    \item{VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format}
    4545        Release of XML specification of the \xcoach format enhanced with
    4646        the expression of loop potential.
    47     \item{-2-V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format}
     47    \item{V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format}
    4848        The first executable generates a \xcoach description
    4949        version \taskname-3-V1 from a C++ description of a task defined in \ST
    … …  
    5151        The second program regenerates a C description from a \xcoach
    5252        description.
    53     \item{-2-VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format}
     53    \item{VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format}
    5454        \global\edef\STcTOxcoach{\name}
    5555        The same programs as the former but for \xcoach format version \name-3-V2.
    56     \item{-3-V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC}
     56    \item{V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC}
    5757        The first release of a program that translates \xcoach description to CABA
    5858        and TLM-DT SystemC.
    59     \item{-3-VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC}
     59    \item{VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC}
    6060        \global\edef\STxcoachTOsystemc{\name}
    6161        The \name-3-V1 deliverable without bugs reported by the demonstrators.
    62     \item{-4-V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL}
     62    \item{V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL}
    6363        The first release of a program that translates \xcoach description to
    6464        synthesizable VHDL description.
    65     \item{-4-VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL}
     65    \item{VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL}
    6666        \global\edef\STxcoachTOvhdl{\name}
    6767        The \name-4-V1 deliverable without bugs reported by the demonstrators.
    … …  
    7373    and by extracting their delays. This is done by using RTL synthesis.
    7474    \begin{livrable}
    75     \item{-1-VF}{0}{6}{d}{\Subs}{macro-cell definition}
     75    \item{}{0}{6}{d}{\Subs}{macro-cell definition}
    7676        The document define the macro cell and the file format describing them.
    77     \item{-2-VF}{0}{12}{x}{\Subs}{macro-cell library generator}
     77    \item{}{0}{12}{x}{\Subs}{macro-cell library generator}
    7878        A progam that generates automatically the characterized macro-cell library
    7979        for a FPGA device.

  • anr/task-2.tex

    r28 r35  
    2525\item This \ST corresponds to the Coach System Generator (DSG) software.
    2626    \begin{livrable}
    27     \item{-V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
     27    \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
    2828        start working using the COACH hardware architecture template.
    29     \item{-V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
     29    \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
    3030        and Altera architectural templates and to the enhanced communication system.
    31     \item{-VF}{0}{36}{x}{\Supmc}{DSG} The final release.
     31    \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release.
    3232    \end{livrable}
    3333\item This \ST relies to the components of the Coach architectural template.
    3434    \begin{livrable}
    35     \item{-VF}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
     35    \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
    3636        of the SocLib MWMR, TokenRing.
    3737    \end{livrable}
    … …  
    4040    communication schems.
    4141    \begin{livrable}
    42     \item{-V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
    43     \item{-V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
    44     \item{-VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
     42    \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
     43    \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
     44    \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
    4545    \end{livrable}
    4646\item This \ST consists of the configuration of the SocLib DNA operating system and the
    … …  
    4848    communication schems.
    4949    \begin{livrable}
    50     \item{-V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
    51     \item{-V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
    52     \item{-VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
     50    \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
     51    \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
     52    \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
    5353    \end{livrable}
    5454\item This \ST relies to definition and implementation of the enhanced communication
    5555    schems usable in the definition of communicante task graph.
    5656    \begin{livrable}
    57     \item{-VF}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
     57    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
    5858        graph inputs (task graph, task description, communication schems).
    5959    \end{livrable}
    … …  
    6161    architectural template.
    6262    \begin{livrable}
    63     \item{-1-VF}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
     63    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
    6464        SystemC model of the MWMR with a PLB bus interface.
    65     \item{-2-VF}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
     65    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
    6666        SystemC model of the MWMR with an AVALON bus interface.
    6767    \end{livrable}

  • anr/task-3.tex

    r28 r35  
    1313    \mustbecompleted{FIXME:IRISA ........}
    1414    \begin{livrable}
    15         \item{-V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
    16         \item{-VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
     15        \item{V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
     16        \item{VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
    1717    \end{livrable}
    1818\item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
    1919    \begin{livrable}
    20         \item{-V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
     20        \item{V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
    2121    \end{livrable}
    2222\end{workpackage}

  • anr/task-4.tex

    r28 r35  
    3030    them by \xcoach and \xcoachplus drivers.
    3131    \begin{livrable}
    32     \item{-V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read
     32    \item{V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read
    3333        \xcoach format.
    34     \item{-VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read
     34    \item{VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read
    3535        \xcoach format and to write \xcoachplus format.
    3636    \end{livrable}
    … …  
    3939    them by \xcoach and \xcoachplus drivers.
    4040    \begin{livrable}
    41     \item{-V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read
     41    \item{V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read
    4242        \xcoach format.
    43     \item{-VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read
     43    \item{VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read
    4444        \xcoach format and to write \xcoachplus format.
    4545    \end{livrable}
    … …  
    4848    usefull enhancements
    4949    \begin{livrable}
    50     \item{-1-VF}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat
     50    \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat
    5151        automatically data dominated sections included into a control dominated application.
    52     \item{-2-VF}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to
     52    \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to
    5353        generate an micro-architecture without the varaiable binding currently done by the
    5454        designer.
    55     \item{-3-VF}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to
     55    \item{}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to
    5656        \mustbecompleted{FIXME:UBS: ........}.
    57     \item{-4-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
     57    \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
    5858        \mustbecompleted{FIXME:UBS: ........}.
    59     \item{-5-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
     59    \item{}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
    6060        \mustbecompleted{FIXME:UBS: ........}.
    6161    \end{livrable}
    … …  
    6969    synthesis.
    7070    \begin{livrable}
    71     \item{-V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of
     71    \item{V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of
    7272        the coprocessor frequency calibration.
    73     \item{-V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware
     73    \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware
    7474        added to the coprocessor to enable the calibration.
    75     \item{-V3}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software
     75    \item{VF}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software
    7676        consists of a driver in the FPGA-SoC operating system and of a control software on
    7777        a PC.

  • anr/task-5.tex

    r29 r35  
    3939    part and FPGA-SoC).
    4040    \begin{livrable}
    41     \item{-1-VF}{0}{21}{x}{\Supmc}{HPC API for Linux PC}
    42     \item{-2-VF}{0}{21}{x}{\Stima}{HPC API for DNA OS}
    43     \item{-3-VF}{0}{21}{x}{\Supmc}{HPC API for Mutek OS}
     41    \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC}
     42    \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS}
     43    \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS}
    4444    \end{livrable}
    4545\item This \ST aims with the implementation of hardware required by the COACH
    4646    architectural template for using the PCI/X IP of \altera and \xilinx.
    4747    \begin{livrable}
    48     \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
     48    \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
    4949        of a PLB/VCI bridge.
    50     \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
     50    \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
    5151        of a AVALON/VCI bridge.
    5252    \end{livrable}
    5353\item This \ST aims with the dynamic reconfiguration of FPGA.
    5454    \begin{livrable}
    55     \item{-1-VF}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
    56     \item{-2-VF}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
    57     \item{-3-VF}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
    58     \item{-3-VF}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
     55    \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
     56    \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
     57    \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
     58    \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
    5959    \end{livrable}
    6060\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    … …  
    6262    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    6363    \begin{livrable}
    64     \item{-VF}{0}{6}{x}{\Saltera}{HPC development boards}
     64    \item{}{0}{6}{x}{\Saltera}{HPC development boards}
    6565    \end{livrable}
    6666\end{workpackage}

  • anr/task-6.tex

    r28 r35  
    1818    or a database management system.
    1919    \begin{livrable}
    20     \item{-V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its
     20    \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its
    2121    implementation as a PC C/C++ program.
    22     \item{-VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator
     22    \item{VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator
    2323    splited into 2 parts, a description as communicante task graph of the FPGA-SoC part.
    2424    \end{livrable}
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