Changeset 35 for anr/task-2.tex

Timestamp:

Jan 15, 2010, 2:33:20 PM (15 years ago)

Author:

coach

Message:

 

File:

• anr/task-2.tex (modified) (4 diffs)

anr/task-2.tex

@@ -25 +25 @@
 \item This \ST corresponds to the Coach System Generator (DSG) software.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
+    \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
         start working using the COACH hardware architecture template.
-    \item{-V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
+    \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
         and Altera architectural templates and to the enhanced communication system.
-    \item{-VF}{0}{36}{x}{\Supmc}{DSG} The final release.
+    \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release.
     \end{livrable}
 \item This \ST relies to the components of the Coach architectural template.
     \begin{livrable}
-    \item{-VF}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
+    \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
         of the SocLib MWMR, TokenRing.
     \end{livrable}
@@ -40 +40 @@
     communication schems.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
-    \item{-V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
-    \item{-VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
+    \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
+    \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
+    \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
     \end{livrable}
 \item This \ST consists of the configuration of the SocLib DNA operating system and the
@@ -48 +48 @@
     communication schems.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
-    \item{-V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
-    \item{-VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
+    \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
+    \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
+    \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
     \end{livrable}
 \item This \ST relies to definition and implementation of the enhanced communication
     schems usable in the definition of communicante task graph.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
+    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
         graph inputs (task graph, task description, communication schems). 
     \end{livrable}
@@ -61 +61 @@
     architectural template.
     \begin{livrable}
-    \item{-1-VF}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
+    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
         SystemC model of the MWMR with a PLB bus interface.
-    \item{-2-VF}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
+    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
         SystemC model of the MWMR with an AVALON bus interface.
     \end{livrable}