Changeset 35 for anr/task-5.tex

Timestamp:

Jan 15, 2010, 2:33:20 PM (15 years ago)

Author:

coach

Message:

 

File:

• anr/task-5.tex (modified) (2 diffs)

anr/task-5.tex

@@ -39 +39 @@
     part and FPGA-SoC).
     \begin{livrable}
-    \item{-1-VF}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 
-    \item{-2-VF}{0}{21}{x}{\Stima}{HPC API for DNA OS} 
-    \item{-3-VF}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 
+    \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 
+    \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS} 
+    \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 
     \end{livrable}
 \item This \ST aims with the implementation of hardware required by the COACH
     architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
+    \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
         of a PLB/VCI bridge.
-    \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
+    \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
         of a AVALON/VCI bridge.
     \end{livrable}
 \item This \ST aims with the dynamic reconfiguration of FPGA.
     \begin{livrable}
-    \item{-1-VF}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
-    \item{-2-VF}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
-    \item{-3-VF}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
-    \item{-3-VF}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
+    \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
+    \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
+    \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
+    \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
     \end{livrable}
 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
@@ -62 +62 @@
     They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
     \begin{livrable}
-    \item{-VF}{0}{6}{x}{\Saltera}{HPC development boards}
+    \item{}{0}{6}{x}{\Saltera}{HPC development boards}
     \end{livrable}
 \end{workpackage}