Changeset 356 for anr/section-dissemination.tex
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- Feb 6, 2011, 2:29:09 PM (14 years ago)
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anr/section-dissemination.tex
r324 r356 23 23 The COACH project will bring new scientific results in various fields, such as high level synthesis, 24 24 hardware/software codesign, virtual prototyping, hardware oriented compilation techniques, 25 automatic paralleli sation, etc. These results will be published in relevant International25 automatic parallelization, etc. These results will be published in relevant International 26 26 Conferences, namely DATE, DAC, or ICCAD. 27 27 \\ 28 28 More generally, the COACH infrastructure and the design flow supported by the COACH 29 29 tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis 30 in various wor shops and conferences (DATE, DAC, CODES+ISSS...).31 30 in various workshops and conferences (DATE, DAC, CODES+ISSS...). 31 \parlf 32 32 Several COACH partners being members of the HiPEAC European Network of Excellence 33 33 (High Performance and Embedded Architecture and Compilation), courses will be proposed for the 34 34 HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems. 35 36 Following the general policy of the SoCLib platform, the COACH project will be an 37 open infrastructure, and the COACH tools and libraries will be available in the framework 38 of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. 39 35 \parlf 36 The COACH project will be an open infrastructure, and the COACH tools and libraries will be available via 37 a WEB server. This server will be maintained by the UPMC/LIP6 laboratory. 38 \\ 40 39 On the standardization side, some effort will be made for analysing how the work around IP-XACT 41 could be donated for the evolution of the IEEE 1685 standard. Magillemis board member of40 could be donated for the evolution of the IEEE 1685 standard. \mds is board member of 42 41 Accellera, TRT, TIMA and LIP6 are members, so we'll try to have some influence and at least 43 42 communicate on the fact that our solutions will be compatible with the standard. … … 56 55 All software tools supporting the COACH design flow will be available as free software. 57 56 All academic partners contributing to the COACH project agreed to distribute the ESL software 58 tools under the same GPL license as the SoCLib tools.57 tools under the same GPL license. 59 58 \item 60 59 The SystemC simulation models for the hardware components … … 75 74 synthesis tools developed in the COACH project. 76 75 \item 77 \mds will propose a commercial version of COACH, integrated into Magillem tool suite and compatible with a standard IP-XACT flow. 78 This version will integrate some generic features, already available for production (some of them from standard Magillem pack, some other developped in COACH). Other COACH features will have to be tailored for the specifics of the customer framework and will generate service business. 76 \mds will propose a commercial version of COACH, integrated into \mds tool suite and compatible with a standard IP-XACT flow. 77 This version will integrate some generic features, already available for 78 production (some of them from standard \mds pack, some other developed in 79 COACH). Other COACH features will have to be tailored for the specifics of the 80 customer framework and will generate service business. 79 81 \end{itemize} 80 82 … … 88 90 The interest for \mds in this project is multiple. 89 91 \begin{itemize} 90 \item We will collaborate in experiments for the integration of High Level Synthesis engines into IP-XACT based flow. 91 This point will be very valuable because more and more system integrators are using or considering to use 92 HLS in their flow (e.g. Astrium, Airbus, etc.) 93 \item \mds has already a leading position in the usage of IP-XACT standard for managing innovative SoC design 94 methodologies. This project will allow to keep the advance in regards with competition by anticipating 95 the next generation platforms hosting mutli cores and programmable logic for coprocessors. 96 \item HPC is a topic that was not covered yet by \mds with its customers. Thanks to this project, \mds will 97 collaborate with BULL on this point and this will open us doors for new customers market. 98 \item This project has been set up for maximizing the industrial exploitation of results. The role of \mds will 99 be to ensure this objective and after the project, we expect a growing contribution for rising the turnover (2015: 2 new customers = 100keuros, 100 2016: 4 new customers = 250keuros, 2017: 5 new customers = 400Keuros). These numbers are not high but we tried to keep them realistic. 101 The return on investment is nevertheless important and we can also expect side effects of this project on sales with existing 102 customers and prospects interrested in the global magillem solution. 92 \item 93 We will collaborate in experiments for the integration of High Level Synthesis 94 engines into IP-XACT based flow. This point will be very valuable because more 95 and more system integrators are using or considering to use HLS in their flow 96 (e.g. Astrium, Airbus, etc.). 97 \item 98 \mds has already a leading position in the usage of IP-XACT standard for 99 managing innovative SoC design methodologies. This project will allow to keep 100 the advance in regards with competition by anticipating the next generation 101 platforms hosting multi-cores and programmable logic for coprocessors. 102 \item 103 HPC is a topic that was not covered yet by \mds with its customers. Thanks to 104 this project, \mds will collaborate with BULL on this point and this will open 105 us doors for new customers market. 106 \item 107 This project has been set up for maximizing the industrial exploitation of results. 108 The role of \mds will be to ensure this objective and after the project, we 109 expect a growing contribution for rising the turnover 110 (2015: 2 new customers = 100 k\euro, 111 2016: 4 new customers = 250 k\euro, 112 2017: 5 new customers = 400 k\euro). 113 These numbers are not high but we tried to keep them realistic. 114 The return on investment is nevertheless important and we can also expect side 115 effects of this project on sales with existing customers and prospects 116 interested in the global \mds solution. 103 117 \end{itemize} 104 118 … … 108 122 HPC solutions. The main expectation from COACH is to derive a new component (fine-grain 109 123 FPGA parallelism) to add to existing Bull HPC solutions. 110 111 %\subsubsection*{Partner: \textit{\xilinx}}112 %Computing power potential of our FPGA architectures113 %growing very quickly on one side, and complexity of designs implemented114 %using our FPGAs dramatically increasing on the other side, it is very115 %interesting for us to get high level design methodologies progressing116 %quickly and targetting our FPGAs in the most possible efficient way.117 %\parlf118 %\xilinx goal is to get COACH to generate bitstream optimized as much as possible for119 %\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease120 %future work of our customers.121 124 122 125 \subsubsection*{Partner: \textit{\thales}}
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