Changeset 362 for anr

Timestamp:

Feb 8, 2011, 4:43:51 PM (13 years ago)

Author:

coach

Message:

IA: entree de UBS.

Location:

anr

Files:

• annexe-autre-participation.tex (modified) (1 diff)
• annexe-cv.tex (modified) (2 diffs)
• anr.bib (modified) (1 diff)
• section-ressources.tex (modified) (1 diff)

anr/annexe-autre-participation.tex

@@ -95 +95 @@
     {\makebox{Dominique Lavenier} (IRISA)}
     {01/01/2009 31/12/2011}
+\autreprojettabularentry
+    {3}{Coussy}{3}
+    {SoCKeT, FUI, 177 k\euro}
+    {SoC toolKit for critical Embedded sysTems}
+    {\makebox{Coordinator Vincent LEFFTZ} (Astrium)}
+    {01/06/2008 31/12/2011}
 \end{autreprojettabular}
 %

anr/annexe-cv.tex

@@ -156 +156 @@
   {Associate Professor}
   {PhD (2003)}
-  {{47}{\cite{COUSSY:2005:HAL-00077301:1} \cite{IEEEDT} \cite{HLSBOOK}
-  \cite{DBLP:journals:dt:CoussyT09} \cite{gaut08} \cite{gaut08} \cite{DBLP:journals:dt:CoussyGMT09} \cite{DBLP:journals:vlsisp:ThabetCHM09}}}
+  {{47}{ \cite{5605303} \cite{gaut08} \cite{HLSBOOK} \cite{DBLP:journals:dt:CoussyGMT09}
+         \cite{DBLP:journals:vlsisp:ThabetCHM09}}}
   \item[Course of Lectures]\mbox{}
        Computer Architecture, programming language, operating systems,
@@ -175 +175 @@
   {Associate Professor}
   {PhD (2007)}
-{{20}{\cite{CHAVET:2007:HAL-00153994:1} \cite{DBLP:conf:iccad:ChavetACCJUM07} \cite{DBLP:conf:glvlsi:ChavetCUM07}}}
+{{20}{\cite{CHAVET:2007:HAL-00153994:1} \cite{DBLP:conf:iccad:ChavetACCJUM07}
+\cite{DBLP:conf:glvlsi:ChavetCUM07} \cite{5605303}}}
   \item[Course of Lectures]\mbox{}
        Parrallel programming, VHDL, real time programming, database networking 

anr/anr.bib

@@ -401 +401 @@
 }
 
+@ARTICLE{5605303,
+  author={Andriamisaina, C. and Coussy, P. and Casseau, E. and Chavet, C.},
+  journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, title={High-Level Synthesis for Designing Multimode Architectures},
+  year={2010},
+  month={nov.},
+  volume={29},
+  number={11},
+  pages={1736 -1749},
+  keywords={GAUT;associated high-level synthesis tool;controller complexity;digital signal processing;image processing;joint-scheduling algorithm;monomode architectures;multimode architecture design;single register transfer level hardware architecture;specific binding approach;high level synthesis;reconfigurable architectures;scheduling;},
+  doi={10.1109/TCAD.2010.2062751},
+  ISSN={0278-0070},
+}
 
 

anr/section-ressources.tex

@@ -168 +168 @@
   {ubs}
   {}
-  {{\ubs}{48}{24}{Philippe COUSSY, Cyrille CHAVET and Dominique HELLER}{83}{
-   \mustbecompleted{\\UBS: A) manque 1 profil ici, B) dans annexe 7.2 il ne faut que 5
-   publis de moins de 5 ans, C) Vous n'etes dans aucuns projets annexe 7.3 ?}
+  {{\ubs}{48}{24}{Philippe COUSSY, Cyrille CHAVET and Dominique HELLER}{84}{
+   We are looking for profiles with strong informatic skills, good knowledge
+   in computer architecture and advanced digital design.
    \mustbecompleted{\\UBS:  ./gantt < anr.gant\\
    \t WARNING: ubs       :D511 probleme sur l'an 1 (in table=7.0, in gantt=6.0 \\
    \t ERROR:   ubs       :D840 probleme sur l'an 1 (in table=0.5, in gantt=0.0}
   }}
-  {10}{4}
+  {11}{4}
 
 % \begin {description}