- Timestamp:
- Feb 8, 2011, 1:10:35 AM (14 years ago)
- Location:
- anr
- Files:
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- 2 added
- 9 edited
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anr/annexe-autre-participation.tex
r360 r361 25 25 \autreprojettabularentry 26 26 {2}{Greiner}{4} 27 {Tsar, CATRENE, 695k\euro}27 {Tsar, CATRENE, 400 k\euro} 28 28 {Tera Scale ARchitecture} 29 29 {\makebox{Huy-Nam} Nguyen (Bull)} -
anr/annexe-cv.tex
r360 r361 56 56 {{Nguyen}{Huy-Nam}{56}} 57 57 {Head of MVS Departement at Bull S.A.S} 58 {Thesis (19 77), ENSMP Engineer (1977)}58 {Thesis (1982), ENSMP Engineer (1977)} 59 59 {{5}{}} 60 60 \item[Projects]\mbox{} … … 92 92 \item[Course of Lectures]\mbox{} 93 93 Compilers, programming languages, computer architecture, networks. 94 \item[Projects]\mbox{}95 \begin{itemize}96 \item Nano2012 S2S4HLS, 2009--97 \end{itemize}98 94 \end{cvenv} 99 95 % … … 204 200 % 205 201 \begin{cvenv} 206 {{Lemon ier}{Fabrice}{43}}202 {{Lemonnier}{Fabrice}{43}} 207 203 {Research program manager} 208 204 {PhD (1996), Master in parallel computing (1992), EFREI Engineer (1991)} -
anr/anr.sty
r356 r361 29 29 \immediate\write\@auxout{\expandafter\string\expandafter\gdef\expandafter\string\csname NOVL#1\endcsname{\@novers{\name}}}% 30 30 #2} 31 32 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 33 %\AtBeginDocument{ 34 % \renewcommand{\@listi}{ 35 % \setlength{\leftmargin}{\leftmargini} 36 % \setlength{\topsep} {2pt} 37 % \setlength{\parsep} {\parskip} 38 % \setlength{\itemsep}{3pt}} 39 % \renewcommand{\@listii}{ 40 % \setlength{\leftmargin}{\leftmarginii} 41 % \setlength{\topsep} {1pt} 42 % \setlength{\parsep} {0pt} 43 % \setlength{\itemsep}{1pt}} 44 % \renewcommand{\@listiii}{ 45 % \setlength{\leftmargin}{\leftmarginiii} 46 % \setlength{\topsep} {1pt} 47 % \setlength{\parsep} {0pt} 48 % \setlength{\itemsep}{1pt}} 49 %} 50 31 51 32 52 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -
anr/section-2.tex
r356 r361 21 21 %based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. 22 22 %%% 23 \parlf 23 % 24 24 The COACH project will propose a new design flow based on a small number of architectural templates. 25 25 An architectural template is a generic, parameterized architecture, relying on a predefined library … … 63 63 %%those various technologies, and to define the detailed architecture of the proposed design flow. 64 64 %%%% 65 \parlf 65 % 66 66 In HPC (High Performance Computing), the targeted application is an existing one 67 67 running on a PC. -
anr/section-consortium-desc.tex
r356 r361 223 223 them in the transformation of their information systems and to optimize their IT 224 224 infrastructure and their applications. 225 \ parlf225 \\%\parlf 226 226 \bull is particularly present in the public sector, banking, finance, telecommunication 227 227 and industry sectors. Capitalizing on its wide experience, the Group has a thorough … … 262 262 %technologies including man system interaction. 263 263 The Embedded System Laboratory (ESL) involved in the COACH project is part of 264 TRT, it is based in Centres(France).264 TRT, it is based in Palaiseau (France). 265 265 \parlf 266 266 Like other labs of TRT, ESL is in charge of making the link between the needs -
anr/section-consortium-people.tex
r360 r361 81 81 %\end{peopletabular}\begin{peopletabular} 82 82 \peopletabularentry{\ubs} 83 \RE & Coussy & Philippe & \mbox{\AP} & SOC HLS \ARCH \VP & 12 & Task: 1, 2, \TL{5}, \mustbecompleted{X, Y},8 \\\hline84 \ME & Heller & Dominique & \mbox{\RENG} & \COMP HLS \ARCH & 8 & Task: \mustbecompleted{X, Y}\\\hline85 \ME & Chavet & Cyrille & \mbox{\AP} & SOC HLS \ARCH & 4 & Task: \mustbecompleted{X, Y}\\\hline83 \RE & Coussy & Philippe & \mbox{\AP} & SOC HLS \ARCH \VP & 12 & Task: 1, 2, \TL{5}, 8 \\\hline 84 \ME & Heller & Dominique & \mbox{\RENG} & \COMP HLS \ARCH & 8 & Task: 2, 5, 8 \\\hline 85 \ME & Chavet & Cyrille & \mbox{\AP} & SOC HLS \ARCH & 4 & Task: 2, 5, 8 \\\hline 86 86 %\end{peopletabular}\begin{peopletabular} 87 87 \peopletabularentry{\liplong} 88 \RE & Alias & Christophe & \mbox{\INRE} & \COMP HPC \MM & 1 5 & Task: 1, 2, \TL{4}, 8 \mustbecompleted{X, Y}\\\hline89 \ME & Feautrier & Paul & \mbox{\EP} & \COMP \AUPA & 1 3 & Task: \mustbecompleted{X, Y}\\\hline88 \RE & Alias & Christophe & \mbox{\INRE} & \COMP HPC \MM & 13 & Task: 1, 2, \TL{4}, 8 \\\hline 89 \ME & Feautrier & Paul & \mbox{\EP} & \COMP \AUPA & 12 & Task: 2, 4, 7, 8 \\\hline 90 90 %\end{peopletabular}\begin{peopletabular} 91 91 \peopletabularentry{\tima} … … 95 95 %\end{peopletabular}\begin{peopletabular} 96 96 \peopletabularentry{\inria} 97 \RE & Charot & François & \mbox{\INRE} & SOC ASIP \ARCH & 12& Task: 1, 2, 4, 8 \\\hline98 \ME & Derrien & Steven & \mbox{\AP} & HLS \COMP\ARCH & 6& Task: 2, 4, 8\\\hline97 \RE & Charot & François & \mbox{\INRE} & SOC ASIP \ARCH & \mustbecompleted{12} & Task: 1, 2, 4, 8 \\\hline 98 \ME & Derrien & Steven & \mbox{\AP} & HLS \COMP\ARCH & \mustbecompleted{6} & Task: 2, 4, 8\\\hline 99 99 %\end{peopletabular}\begin{peopletabular} 100 100 \peopletabularentry{\bull} … … 102 102 %\end{peopletabular}\begin{peopletabular} 103 103 \peopletabularentry{\thales} 104 \RE & Lemon ier & Fabrice & \DM & SOC & 18 & Task: \mustbecompleted{X, Y} \TL{7}\\\hline104 \RE & Lemonnier & Fabrice & \DM & SOC ARCH & 7 & Task: 1, \TL{7}, 8 \\\hline 105 105 \ME & Brelet & Paul & \mbox{SW\,development} 106 & \SW & 18 & Task: 7,8 \\\hline106 & \SW & 8 & Task: 7,8 \\\hline 107 107 \end{peopletabular} 108 108 \caption{\label{involved:people} People that participate to the project.} -
anr/section-dissemination.tex
r356 r361 118 118 119 119 \subsubsection*{Partner: \textit{\bull}} 120 The team of \bull participating to the COACH project is from the Server Development 121 Department who is in charge of developing hardware for open servers (e.g. NovaScale) and 122 HPC solutions. The main expectation from COACH is to derive a new component (fine-grain 123 FPGA parallelism) to add to existing Bull HPC solutions. 120 \noindent 121 The Bull team participating to COACH is from the Server Design and Development Division, 122 who is in charge of developing hardware for open servers (e.g.: NovaSacle, Bullion) and 123 HPC solutions. With this participation, Bull demonstrates its high interest in the outcome of 124 COACH. Effectively, it is now commonly recognized that the future of HPC will be based 125 on hybrid architectures in which FPGA will play a major role in the development of configurable 126 hardware accelerators by providing the best fine grain parallelism. 124 127 125 128 \subsubsection*{Partner: \textit{\thales}} … … 137 140 synthesis of system embedding control and data flow aspects. 138 141 \end{itemize} 139 \parlf 142 % 140 143 TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging 141 144 technologies in its domains of expertise. Specifically in COACH, the studied technology is … … 158 161 \subsubsection*{Industrial supports} 159 162 160 \mustbecompleted{NON A JOUR}161 163 The following SMEs demonstrate interest to the COACH project (see the "letters of 162 164 interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will … … 164 166 \letterOfInterest{ALTERA Corporation}{lettres-2011/Altera1.pdf}, 165 167 \letterOfInterestPlus{lettres-2011/Altera2.pdf} 168 \letterOfInterest{FlexRAS Technologies}{lettres-2011/Flexras.pdf}, 169 \letterOfInterest{INPIXAL}{lettres-2011/Inpixal.jpg}, 166 170 %\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet}, 167 %\letterOfInterest{INPIXAL}{lettres-2011/inpixal.jpg},168 171 %\letterOfInterest{CAMKA System}{lettres-2011/CAMKA-System.pdf}, 169 172 %\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf}, -
anr/section-ressources.tex
r360 r361 127 127 \ressourcesForAcademic 128 128 {upmc} 129 { In order to validate the COACH design flow, \upmc will buy FPGA development 130 boards (especially 1 PCI/E FPGA \xilinx board). 131 The cost for these boards is estimated to 4500 \euro (3\% of the total ANR funding).} 132 {{\upmc}{52}{24}{Alain Greiner and Ivan Aug\'e}{87}{ 129 {} 130 {{\upmc}{52}{24}{Alain Greiner and Ivan Aug\'e}{88}{ 133 131 We are looking for a profile with strong skills in SW development and good 134 132 knowledge in SoC design and virtual prototyping. 135 133 }} 136 { 7}{3.5}134 {8}{3.5} 137 135 % 138 136 % \begin{description} … … 169 167 \ressourcesForAcademic 170 168 {ubs} 171 { In order to validate the design flow project, the Lab-STICC laboratory will buy FPGA 172 development boards. The cost for these FPGA boards is estimated to 3\% of the total 173 ANR funding. 174 \mustbecompleted{INCOHERENCE avec SITE ANR} 175 } 169 {} 176 170 {{\ubs}{48}{24}{Philippe COUSSY, Cyrille CHAVET and Dominique HELLER}{83}{ 177 171 \mustbecompleted{\\UBS: A) manque 1 profil ici, B) dans annexe 7.2 il ne faut que 5 … … 215 209 \ressourcesForAcademic 216 210 {inria_compsys}{} 217 {{\lip}{46}{2 2}{Christophe Alias and Paul Feautrier}{100}{211 {{\lip}{46}{21}{Christophe Alias and Paul Feautrier}{\mustbecompleted{100}}{ 218 212 \\We are looking for a candidate with both theoretical and 219 213 practical skills, that will be able to get a sufficient 220 214 understanding of the polyhedral techniques. 221 \mustbecompleted{\\LIP: DANS FIG.8 vous avez 28 hm. 46-28=18 --> 40\%\\222 IL FAUT ETRE <= 50\%, le max de non permanent est 23.}223 \mustbecompleted{\\LIP: Vous n'etes dans aucuns projets annexe 7.3 ?}224 215 \mustbecompleted{\\LIP: ./gantt < anr.gant\\ 225 216 \t WARNING: lip :D432 probleme sur l'an 2 (in table=7.0, in gantt=6.0 \\ … … 227 218 \t ERROR: lip :D730 probleme sur l'an 3 (in table=0.0, in gantt=3.0} 228 219 }} 229 { \mustbecompleted{(LIP: ca fait beaucoup) }20}{4}220 {12}{4} 230 221 % 231 222 % \begin{description} … … 315 306 We are looking for a profile with strong skills in SW development and good 316 307 knowledge in computer architecture. 317 % \mustbecompleted{\\IRISA figure 8 vous avez 18 hm vous devez avoir 22.} 318 % \mustbecompleted{\\IRISA: Vous n'etes dans aucuns projets annexe 7.3 ?}% 319 % \mustbecompleted{\\IRISA: ./gantt < anr.gant\\ 320 % \t ERROR: inria :D420 probleme sur l'an 3 (in table=0.0, in gantt=3.0} 308 \mustbecompleted{\\IRISA figure 8 vous avez 18 hm vous devez avoir au moins 23.} 321 309 }} 322 310 {10}{4} … … 355 343 \ressources 356 344 {bull} 357 { Acquisition of a FPGA development board will represent the main equipment cost for358 Bull in COACH. It is estimated at about 5\% (tbc) of the total funding.359 \mustbecompleted{INCOHERENCE avec SITE ANR}360 }345 { The design of FPGA board (s) will represent the main equipment cost for Bull 346 in COACH. It is estimated at about 10 k\euro (about 12\% of the total 347 requested ANR funding) representing the re-design/adaptation of an 348 existing FPGA board (the SAM "Simulation Accelerated Module" board).} 361 349 { 362 350 The man power detail in \hommemois by deliverables is given in … … 392 380 {thales} 393 381 { In order to validate the design flow,TRT will buy FPGA developpement boards. The cost 394 for these FPGA boards is estimated to 11 k\euro (6\% of the total ANR funding). 395 \mustbecompleted{INCOHERENCE avec SITE ANR} 396 } 382 for these FPGA boards is estimated to 11 k\euro (6\% of the total ANR funding).} 397 383 { The man power detail in \hommemois by deliverables is given in 398 annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales}) .384 annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales}) 399 385 and a summary by task in the following table. 400 \thales employees involved in the project are a manager for 18\hommemois401 and an engineer for 18 \hommemois.}386 \thales employees involved in the project are a manager for 7 \hommemois 387 and an engineer for 8 \hommemois and a PHD candidate for 21 \hommemois} 402 388 {5}{} 403 389 -
anr/task-frontend.tex
r360 r361 45 45 \itemV{0}{12}{x}{\Sinria}{SystemC for extensible MIPS } 46 46 { A SystemC simulation model for a simple extensible MIPS architectural template } 47 \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3: 3:0}47 \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3:2:1} 48 48 {A SystemC simulation model for an extensible MIPS with a tight architectural integration of 49 49 its instruction set extensions}
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