Changeset 363 for anr

Timestamp:

Feb 9, 2011, 8:44:36 AM (14 years ago)

Author:

coach

Message:

INRIA : nombre d'hm permanents passé de 18 à 24

Location:

anr

Files:

• section-consortium-people.tex (modified) (1 diff)
• section-ressources.tex (modified) (1 diff)
• task-frontend.tex (modified) (2 diffs)

anr/section-consortium-people.tex

@@ -95 +95 @@
 %\end{peopletabular}\begin{peopletabular}
 \peopletabularentry{\inria}
-\RE & Charot      & François     & \mbox{\INRE}       & SOC ASIP \ARCH     & \mustbecompleted{12} & Task: 1, 2, 4, 8 \\\hline
-\ME & Derrien      & Steven      & \mbox{\AP}         & HLS \COMP\ARCH     & \mustbecompleted{6} & Task: 2, 4, 8\\\hline
+\RE & Charot      & François     & \mbox{\INRE}       & SOC ASIP \ARCH & 15 & Task: 1, 2, 4, 8 \\\hline
+\ME & Derrien      & Steven      & \mbox{\AP}         & HLS \COMP\ARCH & 9 & Task: 2, 4, 8\\\hline
 %\end{peopletabular}\begin{peopletabular}
 \peopletabularentry{\bull}           

anr/section-ressources.tex

@@ -303 +303 @@
 \ressourcesForAcademic
  {inria_cairn}{}
- {{\inria}{45}{27}{ François Charot and Steven Derrien}{84}{
+ {{\inria}{51}{27}{ François Charot and Steven Derrien}{84}{
     We are looking for a profile with strong skills in SW development and good
     knowledge in computer architecture.
-   \mustbecompleted{\\IRISA figure 8 vous avez 18 hm vous devez avoir au moins 23.}
-    }}
+   }}
  {10}{4}
 % 

anr/task-frontend.tex

@@ -31 +31 @@
         custom instructions are specified by the user, and then automatically extracted (when
         beneficial) from the application intermediate representation. 
-      \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{4:5:3}
+      \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{6:6:3}
         In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
@@ -50 +50 @@
       \itemV{3}{18}{h}{\Sinria}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
-      \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{7:6.5:3}
+      \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{8:8.5:3}
       {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}