Changeset 376 for anr/section-dissemination.tex

Timestamp:

Feb 15, 2011, 1:33:40 PM (14 years ago)

Author:

coach

Message:

minor Paul

M anr/section-dissemination.tex

File:

• anr/section-dissemination.tex (modified) (7 diffs)

anr/section-dissemination.tex

@@ -21 +21 @@
 \subsection{Dissemination}
 
-The COACH project will bring new scientific results in various fields, such as high level synthesis,
+The COACH project will generate new scientific results in various fields, such as high level synthesis,
 hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
 automatic parallelization, etc. These results will be published in relevant International
-Conferences, namely DATE, DAC, or ICCAD. 
+Conferences, for instance DATE, DAC, or ICCAD. 
 \\
 More generally, the COACH infrastructure and the design flow supported by the COACH
@@ -39 +39 @@
 On the standardization side, some effort will be made for analysing how the work around IP-XACT 
 could be donated for the evolution of the IEEE 1685 standard. \mds is board member of
-Accellera, TRT, TIMA and LIP6 are members, so we'll try to have some influence and at least
+Accellera, TRT, TIMA and LIP6 are members, so we will try to have some influence and at least
 communicate on the fact that our solutions will be compatible with the standard.
 
 \subsection{Industrial exploitation of results}
 
-The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) and even small design team in bigger entities
+The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) and even small design team in larger entities
 to enter the world of MPSoC technologies. For small companies or design services, the cost is a primary concern.
-Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
+Moreover, these companies seldom have in-home expertise in hardware design and VHDL modelling.
 As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
 on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) 
@@ -74 +74 @@
 synthesis tools developed in the COACH project.
 \item
-\mds will propose a commercial version of COACH, integrated into \mds tool suite and compatible with a standard IP-XACT flow.
+\mds will propose a commercial version of COACH, integrated into an \mds tool suite and compatible with a standard IP-XACT flow.
 This version will integrate some generic features, already available for
-production (some of them from standard \mds pack, some other developed in
+production (some of them from a standard \mds pack, some other developed in
 COACH). Other COACH features will have to be tailored for the specifics of the
 customer framework and will generate service business.
@@ -93 +93 @@
 We will collaborate in experiments for the integration of High Level Synthesis
 engines into IP-XACT based flow.  This point will be very valuable because more
-and more system integrators are using or considering to use HLS in their flow
+and more system integrators are using or considering the use of HLS in their development flow
 (e.g. Astrium, Airbus, etc.).
 \item
 \mds has already a leading position in the usage of IP-XACT standard for
 managing innovative SoC design methodologies. This project will allow to keep
-the advance in regards with competition by anticipating the next generation
+this competitive advance by anticipating the next generation
 platforms hosting multi-cores and programmable logic for coprocessors.
 \item
 HPC is a topic that was not covered yet by \mds with its customers. Thanks to
 this project, \mds will collaborate with BULL on this point and this will open
-us doors for new customers market.
+doors for new customers market.
 \item
 This project has been set up for maximizing the industrial exploitation of results.
@@ -119 +119 @@
 \subsubsection*{Partner: \textit{\bull}}
 \noindent
-The Bull team participating to COACH is from the Server Design and Development Division,
-who is in charge of developing hardware for open servers (e.g.: NovaSacle, Bullion) and
+The Bull team participating in COACH is from the Server Design and Development Division,
+which is in charge of developing hardware for open servers (e.g.: NovaSacle, Bullion) and
 HPC solutions. With this participation, Bull demonstrates its high interest in the outcome of
 COACH. Effectively, it is now commonly recognized that the future of HPC will be based
@@ -143 +143 @@
 TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
 technologies in its domains of expertise. Specifically in COACH, the studied technology is
-a method and associated tools to make the bridge between application capture at system
+a method and associated tools to bridge the gap between application capture at system
 level and the implementation on heterogeneous distributed computing architectures. The
 main stake for Thales behind this is the future design process that will be applied to its
-system teams in the future for the computation-intensive sensor applications. In a context
-of very instable market of tools for parallel programming, it is important to experiment
+system teams for computation-intensive sensor applications. In a context
+of very unstable market of tools for parallel programming, it is important to experiment
 and demonstrate the candidate technologies.
 \\
@@ -179 +179 @@
 
 \subsection{Management of Intellectual Property}
-A global consortium agreement will be defined during the first six monts of the project.
+A global consortium agreement will be defined during the first six months of the project.
 As already stated, the COACH project has been prepared during one year by a monthly meeting 
 involving the five academic partners. The general free software policy described in the