Changeset 36 for anr/task-2.tex


Ignore:
Timestamp:
Jan 18, 2010, 9:31:49 AM (14 years ago)
Author:
coach
Message:
 
File:
1 edited

Legend:

Unmodified
Added
Removed

  • anr/task-2.tex

    r35 r36  
    77\begin{objectif}
    88This task relies to the prototyping and the generation of FPGA-SoC digital systems.
    9 Its is described on figure~\ref{archi-csg} and it consists of
    10 Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system.
     9Its is described on figure~\ref{archi-csg}.
     10Its objective is to allow the system designer to explore the system space design by
     11quickly prototyping and then to generate automatically the FPGA-SoC system.
    1112This task consists of
    1213\begin{itemize}
    … …  
    1415\item the configuration and the development of drivers of the operating systems,
    1516\item the CSG software that generates the simulators for prototiping and the FPGA-SoC system,
    16 \item the specification of enhanced communication schem and their sofware and hardware implementation.
     17\item the specification of enhanced communication schems and their sofware and hardware implementation.
    1718\end{itemize}
    1819This task being based on the SocLib platform, a first release will be delivrable at $T0+12$
    … …  
    2324%
    2425\begin{workpackage}{D2}
    25 \item This \ST corresponds to the Coach System Generator (DSG) software.
     26\item This \ST corresponds to the Coach System Generator (CSG) software.
    2627    \begin{livrable}
    27     \item{V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
    28         start working using the COACH hardware architecture template.
    29     \item{V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
    30         and Altera architectural templates and to the enhanced communication system.
    31     \item{VF}{0}{36}{x}{\Supmc}{DSG} The final release.
     28    \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
     29        The first milestone that will allow demonstrators to start working using the COACH
     30        hardware architecture template.
     31    \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
     32        This milestone adds to CSG the support to the XILINX and ALTERA architectural
     33        templates and to the enhanced communication system.
     34        In this milestone only the SystemC prototyping will be supported for the XILINX
     35        and ALTERA architectural template.
     36        HAS is available.
     37    \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
     38        This milestone extends CSG (\csgPrototypingOnly) to
     39        FPGA-SoC generation for the XILINX and ALTERA architectural template.
     40    \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG.
    3241    \end{livrable}
    33 \item This \ST relies to the components of the Coach architectural template.
     42\item This \ST relies to the components of the architectural template.
     43    \\
     44    For the COACH architectural template, it consists of the devlopment of the VHDL
     45    synthesizable description of the missing components. Notice that the SystemC models
     46    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
     47    ANR project.
     48    \\
     49    For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs.
     50    The component that miss is the MWMR used for commucation between the task of the
     51    application.
    3452    \begin{livrable}
    35     \item{}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
    36         of the SocLib MWMR, TokenRing.
     53    \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions
     54        of the SocLib MWMR, TokenRing components.
     55    \item{V1}{6}{18}{x}{\Stima}{XILINX architecture}
     56        \setMacroInAuxFile{csgXilinxSystemC}
     57        The SystemC simulation module of the MWMR component with a PLB bus interface plus
     58        the SystemC modules of the components of the XILINX architectural template
     59        not available in the SocLib component library.
     60    \item{VF}{18}{24}{h}{\Stima}{XILINX architecture}
     61        The synthesizable VHDL description of the MWMR component corresponding to the
     62        SystemC module of the former delivrable (\csgXilinxSystemC).
     63    \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture}
     64        \setMacroInAuxFile{csgAlteraSystemC}
     65        The SystemC simulation module of the MWMR component with a AVALON bus interface plus
     66        the SystemC modules of the components of the ALTERA architectural template
     67        not available in the SocLib component library.
     68    \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture}
     69        The synthesizable VHDL description of the MWMR component corresponding to the
     70        SystemC module of the former delivrable (\csgAlteraSystemC);
    3771    \end{livrable}
    38 \item This \ST consists of the configuration of the SocLib Mutek operating system and the
    39     development of drivers for the hardware architectural template and enhanced
    40     communication schems.
     72\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
     73    system and the development of drivers for the hardware architectural templates
     74    and enhanced communication schems defined in \novers{\specCsgManual} delivrable.
     75    For the ALTERA and XILINX architectural template, the OSs must also be ported on
     76    the NIOS2 and MICROBLAZE processors.
    4177    \begin{livrable}
    42     \item{V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
    43     \item{V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
    44     \item{VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
     78    \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG
     79    milestone (delivrable \csgCoachArch).
     80    \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the
     81    second CSG milestone ({\csgPrototypingOnly}).
     82    \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work.
     83    \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS}
     84        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     85    \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG
     86    milestone (delivrable \csgCoachArch).
     87    \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the
     88    second CSG milestone ({\csgPrototypingOnly}).
     89    \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work.
     90    \item{}{6}{18}{x}{\tima}{Port of DNA OS}
     91        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
    4592    \end{livrable}
    46 \item This \ST consists of the configuration of the SocLib DNA operating system and the
    47     development of drivers for the hardware architectural template and enhanced
    48     communication schems.
    49     \begin{livrable}
    50     \item{V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
    51     \item{V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
    52     \item{VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
    53     \end{livrable}
    54 \item This \ST relies to definition and implementation of the enhanced communication
    55     schems usable in the definition of communicante task graph.
    56     \begin{livrable}
    57     \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
    58         graph inputs (task graph, task description, communication schems).
    59     \end{livrable}
    60 \item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
    61     architectural template.
    62     \begin{livrable}
    63     \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
    64         SystemC model of the MWMR with a PLB bus interface.
    65     \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
    66         SystemC model of the MWMR with an AVALON bus interface.
    67     \end{livrable}
     93% moved in task 1
     94%\item This \ST relies to definition and implementation of the enhanced communication
     95%    schems usable in the definition of communicante task graph.
     96%    \begin{livrable}
     97%    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
     98%        graph inputs (task graph, task description, communication schems).
     99%    \end{livrable}
     100%\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
     101%    architectural template.
     102%    \begin{livrable}
     103%    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
     104%        SystemC model of the MWMR with a PLB bus interface.
     105%    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
     106%        SystemC model of the MWMR with an AVALON bus interface.
     107%    \end{livrable}
    68108% FIXME:CITI
    69109\end{workpackage}
Note: See TracChangeset for help on using the changeset viewer.