Changeset 382 for anr


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Timestamp:
Feb 21, 2011, 8:17:55 AM (14 years ago)
Author:
coach
Message:

ia: entree de donnees de Paul + Continental.

Location:
anr
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1 added
5 edited

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  • anr/section-1.tex

    r372 r382  
    55%ceci semble vouloir dire que le problÚme de la HLS est résolu pour les ASIC, et que ce que COACH veut faire c'est adapter aux
    66%FPGAs. Ca me paraît à la fois faux et dangereux. Paul
    7 Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both SMES and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest in IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a few years, such chips will surely be used in embedded systems and even standard general purpose CPU cores will contains a configurable area %
    8 %incompréhensible Paul
    9 making explode the low and medium volume markets of digital systems.
     7Unfortunately, ESL tool development today has primarily focused on the design of
     8hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
     9However, the increasing sophistication of FPGAs has accelerated the need for
     10FPGA-based ESL design methodologies. ESL methodologies hold the promise of
     11streamlining the design approach by accepting designs written in C/C++ language
     12and implementing the function straight into FPGA. Coupling FPGA technologies and
     13ESL methodologies will allow both SMES and major companies to design innovative
     14devices and to enter new, low and medium volume markets. Furthermore, today
     15there is an increasing industrial interest in IC that integrates both hardwired
     16CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a
     17few years, such chips will surely be used in embedded systems and even standard
     18general purpose CPU cores will contains a configurable area.
     19This will make possible to target low and medium volume markets of digital
     20system and probably explode the indusrial activity of this markets.
    1021\parlf
    1122COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project do not hope to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system.
    … …  
    2435have expressed their interest for this project:
    2536\altera, FLEXRAS, INPIXAL, CAMKA System, RENESAS Design, EADS-ASTRIUM,
    26 \mustbecompleted{ ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
     37CONTINENTAl,
     38\mustbecompleted{ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
    2739\altera, a major FPGA company provides FPGA cards to the project.
    2840These companies are either FPGA providers (engaged to collaborate by delivering FPGA board to partners),

  • anr/section-2.tex

    r373 r382  
    11Embedded systems (SoC and MPSoC) have become an inevitable evolution in the microelectronic industry.
    22The ASIC technology (Application Specific Integrated Circuits)
    3 is not an option for markets with small series of products due to ROI. % ROI? Return On Investment? Qu'est-ce que ça vien faire? Paul
     3is not an option for markets with small series of products due to RNE costs.
    44Fortunately, the new FPGA (Field Programmable Gate Array) components,
    55such as the Virtex6 family from \xilinx, or the Stratix4 family from \altera can implement a complete
    … …  
    6767running on a PC.
    6868The COACH framework helps designers to accelerate it by migrating critical parts into a
    69 SoC embedded into an FPGA device plugged to the PC PCI/X bus
    70 %paul On ne sait jamais, ça pourrait être Hyper Transport
    71 (or to any other communication fabric).
     69SoC embedded into an FPGA device plugged to the PC PCI/X bus.
    7270\begin{center}\begin{minipage}{.8\linewidth}\label{HPC:definition}\textit{
    7371The second objective of COACH is to extend the framework for HPC applications.

  • anr/section-dissemination.tex

    r376 r382  
    171171\letterOfInterest{RENESAS Design}{lettres-2011/Renesas-dossier.jpg},
    172172\letterOfInterest{EADS-ASTRIUM}{lettres-2011/Astrium.pdf}.
     173\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
    173174%\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet},
    174175%\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf},

  • anr/section-etat-de-art.tex

    r369 r382  
    5656Thus, much effort is required to develop design tools that translate high level
    5757language programs to FPGA configurations.
    58 Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12}
    59 (DPR, which enables changing a part of the FPGA, while the rest is still working)
    60 appears very interesting for improving HPC performance as well as reducing required area.
    61 
    62 %oui, mais il me semble que COACH ne va rien faire à ce sujet. Est-ce la peine de
    63 %donner des verges pour nous faire battre? En outre, je ne vois pas bien l'intérêt.
    64 %
    65 %Paul
    6658
    6759\subsubsection{System Synthesis}
    … …  
    9284do not provide any facilities to synthesize coprocessors and to simulate the platform
    9385at a high level (SystemC).
    94 A system designer must provide the synthesizable description of its own IP-cores with
    95 a feasible bus interface.%
    96 %qu'est-ce que c'est qu'un ``feasible bus interface''? a *standard* bus interface? Paul
    97 %
    98 Design Space Exploration is thus limited
    99 and SystemC simulation is not possible either at transactional or at cycle
    100 accurate level.
     86A system designer must provide the synthesizable description of its own IP-cores
     87interfaces it to the SoC bus.
     88Design Space Exploration is thus limited and SystemC simulation is not possible
     89either at transactional or at cycle accurate level.
    10190\\
    10291In addition, \xilinx System Generator, XPS and SOPC Builder are closed world

  • anr/section-ressources.tex

    r371 r382  
    7171   The effort due to the non permanent personnels is \textbf{#4} \hommemois
    7272   (\textbf{\the\mycnt\%} of the total effort).
    73    %All non permanent personnel costs are estimated in \hommemois for senior researchers (post-doc or research engineers).
    7473   The requested funding for non permanent personnels is \textbf{#6\%} of the total ANR
    7574   requested funding.
    … …  
    8887those of annexe~\ref{effort:by:partner:livrable} shows this global effort by partner and
    8988deliverables.\\
    90 \textbf{NOTICE:} In these tables and in the following sections the units is the
     89\textbf{NOTICE:} 1) In these tables and in the following sections the units is the
    9190\hommemois of a senior researcher (post-doc or research engineers).
     912) In order to develop and check the FPGA drivers, the partners will by some FPGA boards but
     92their costs being less than 4000 \euro, they are not mentionned in the following
     93sections.
     94
    9295
    9396%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    163166  {bull}
    164167  {}
    165   {
    166     The man power detail in \hommemois by deliverables is given in
     168  { The man power detail in \hommemois by deliverables is given in
    167169    annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull}).
    168170    and a summary by task in the following table.
    … …  
    180182\ressources
    181183  {thales}
    182   { In order to validate the design flow,TRT will buy FPGA developpement boards. The cost
    183 %check. Paul
    184     of each board is less than 4000 k\euro.}
     184  {}
    185185  { The man power detail in \hommemois by deliverables is given in
    186186    annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales})
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