Changeset 382 for anr/section-etat-de-art.tex

Timestamp:

Feb 21, 2011, 8:17:55 AM (14 years ago)

Author:

coach

Message:

ia: entree de donnees de Paul + Continental.

File:

• anr/section-etat-de-art.tex (modified) (2 diffs)

anr/section-etat-de-art.tex

@@ -56 +56 @@
 Thus, much effort is required to develop design tools that translate high level
 language programs to FPGA configurations.
-Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12}
-(DPR, which enables changing a part of the FPGA, while the rest is still working)
-appears very interesting for improving HPC performance as well as reducing required area.
-
-%oui, mais il me semble que COACH ne va rien faire à ce sujet. Est-ce la peine de
-%donner des verges pour nous faire battre? En outre, je ne vois pas bien l'intérêt.
-%
-%Paul
 
 \subsubsection{System Synthesis}
@@ -92 +84 @@
 do not provide any facilities to synthesize coprocessors and to simulate the platform 
 at a high level (SystemC). 
-A system designer must provide the synthesizable description of its own IP-cores with 
-a feasible bus interface.%
-%qu'est-ce que c'est qu'un ``feasible bus interface''? a *standard* bus interface? Paul
-%
-Design Space Exploration is thus limited
-and SystemC simulation is not possible either at transactional or at cycle
-accurate level. 
+A system designer must provide the synthesizable description of its own IP-cores
+interfaces it to the SoC bus.
+Design Space Exploration is thus limited and SystemC simulation is not possible
+either at transactional or at cycle accurate level.
 \\
 In addition, \xilinx System Generator, XPS and SOPC Builder are closed world