Changeset 382 for anr/section-1.tex

Timestamp:

Feb 21, 2011, 8:17:55 AM (14 years ago)

Author:

coach

Message:

ia: entree de donnees de Paul + Continental.

File:

• anr/section-1.tex (modified) (2 diffs)

anr/section-1.tex

@@ -5 +5 @@
 %ceci semble vouloir dire que le problÚme de la HLS est résolu pour les ASIC, et que ce que COACH veut faire c'est adapter aux 
 %FPGAs. Ca me paraît à la fois faux et dangereux. Paul
-Unfortunately, ESL tool development today has primarily focused on the design of hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting designs written in C/C++ language and implementing the function straight into FPGA. Coupling FPGA technologies and ESL methodologies will allow both SMES and major companies to design innovative devices and to enter new, low and medium volume markets. Furthermore, today there is an increasing industrial interest in IC that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a few years, such chips will surely be used in embedded systems and even standard general purpose CPU cores will contains a configurable area %
-%incompréhensible Paul
-making explode the low and medium volume markets of digital systems. 
+Unfortunately, ESL tool development today has primarily focused on the design of
+hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
+However, the increasing sophistication of FPGAs has accelerated the need for
+FPGA-based ESL design methodologies. ESL methodologies hold the promise of
+streamlining the design approach by accepting designs written in C/C++ language
+and implementing the function straight into FPGA. Coupling FPGA technologies and
+ESL methodologies will allow both SMES and major companies to design innovative
+devices and to enter new, low and medium volume markets. Furthermore, today
+there is an increasing industrial interest in IC that integrates both hardwired
+CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a
+few years, such chips will surely be used in embedded systems and even standard
+general purpose CPU cores will contains a configurable area.
+This will make possible to target low and medium volume markets of digital
+system and probably explode the indusrial activity of this markets.
 \parlf
 COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project do not hope to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system. 
@@ -24 +35 @@
 have expressed their interest for this project:
 \altera, FLEXRAS, INPIXAL, CAMKA System, RENESAS Design, EADS-ASTRIUM,
-\mustbecompleted{ ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
+CONTINENTAl,
+\mustbecompleted{ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
 \altera, a major FPGA company provides FPGA cards to the project.
 These companies are either FPGA providers (engaged to collaborate by delivering FPGA board to partners),