Changeset 383 for anr/section-1.tex

Timestamp:

Feb 22, 2011, 11:02:52 AM (14 years ago)

Author:

coach

Message:

ia: qq maj et mise en page finale.

File:

• anr/section-1.tex (modified) (1 diff)

anr/section-1.tex

@@ -2 +2 @@
 The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, recent FPGA components, such as the Virtex5-6 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
 \parlf
-Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow.%
-%ceci semble vouloir dire que le problÚme de la HLS est résolu pour les ASIC, et que ce que COACH veut faire c'est adapter aux 
-%FPGAs. Ca me paraît à la fois faux et dangereux. Paul
+Many applications are initially captured algorithmically in High-Level Languages
+(HLLs) such as C/C++. This has led to growing interest in tools that can provide
+an implementation path directly from HLLs to hardware. Thus, Electronic System
+Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level
+Synthesis...) are now mature and but don’t allow still the full automation of a
+system-level design flow.
 Unfortunately, ESL tool development today has primarily focused on the design of
 hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product).