Changeset 383 for anr/section-etat-de-art.tex

Timestamp:

Feb 22, 2011, 11:02:52 AM (13 years ago)

Author:

coach

Message:

ia: qq maj et mise en page finale.

File:

• anr/section-etat-de-art.tex (modified) (7 diffs)

anr/section-etat-de-art.tex

@@ -93 +93 @@
 Designers can then only generate a synthesized netlist, VHDL/Verilog simulation test 
 bench and custom software library that reflect the hardware configuration.
-
-Consequently, a designer developing an embedded system needs to master four different
+\\
+Consequently, a designer developing an embedded system needs to master four
 design environments:
 \begin{enumerate}
@@ -156 +156 @@
  would be valuable in the
 context of a System Level design exploration tool.
-\par
+\\
 In this context, ASIP design based on Instruction Set Extensions (ISEs) has 
 received a lot of interest~\cite{NIOS2}, as it makes micro-architecture synthesis 
@@ -167 +167 @@
 2.5x), since ISEs performance is generally limited by I/O constraints as 
 they generally rely on the main CPU register file to access data.
-
-% (
-%automaticcaly extraction ISE candidates for application code \cite{CODES04}, 
-%performing efficient instruction selection and/or storage resource (register) 
-%allocation \cite{FPGA08}).  
+\\
 To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of 
 micro-architectural ISE models in which the coupling between the processor micro-architecture
@@ -178 +174 @@
 point of view and do not address the problem of generating synthesizable representations for 
 these models. 
-
+\\
 We therefore strongly believe that there is a need for an open-framework which
 would allow researchers and system designers to :
@@ -201 +197 @@
 data structures. Dependences (exact or conservative) are checked to guarantee
 the legality of the transformation.
-
+\\
 This has lead to the invention of many loop transformations (loop fusion,
 loop splitting, loop skewing, loop interchange, loop unrolling, ...)
@@ -209 +205 @@
 \cite{FP:96,DRV:2000}, in which the combination of two transformations is 
 simply a matrix product.
-
+\\
 Since hardware is inherently parallel, finding parallelism in sequential
 programs in an important prerequisite for HLS. The large FPGA chips of
@@ -215 +211 @@
 The polyhedral model is the ideal tool for finding more parallelism in
 loops.
-
+\\
 As a side effect, it has been observed that the polyhedral model is a useful
 tool for many other optimization, like memory reduction and locality