Changeset 385 for anr/section-1.tex

Timestamp:

Feb 22, 2011, 11:30:07 PM (14 years ago)

Author:

coach

Message:

ia: bull to 24 hm + correction MDS.

File:

• anr/section-1.tex (modified) (2 diffs)

anr/section-1.tex

@@ -6 +6 @@
 an implementation path directly from HLLs to hardware. Thus, Electronic System
 Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level
-Synthesis...) are now mature and but don’t allow still the full automation of a
+Synthesis...) are now mature but don’t allow still the full automation of a
 system-level design flow.
 Unfortunately, ESL tool development today has primarily focused on the design of
@@ -35 +35 @@
 \end{itemize}
 %
-Finally,a large number of SMEs and large companies, (see "letters of interest" Annex \ref{lettre-soutien}),
+Finally, a large number of SMEs and large companies, (see "letters of interest" Annex \ref{lettre-soutien}),
 have expressed their interest for this project:
 \altera, FLEXRAS, INPIXAL, CAMKA System, RENESAS Design, EADS-ASTRIUM,
-CONTINENTAl,
-\mustbecompleted{ADACSYS, ATEME, ALSIM, SILICOMP-AQL, ABOUND Logic.}.\\
-\altera, a major FPGA company provides FPGA cards to the project.
+CONTINENTAl, TEAMCAST, ALSIM.
+\altera, a major FPGA company provides FPGA boards to the project.
 These companies are either FPGA providers (engaged to collaborate by delivering FPGA board to partners),
 design houses, EDA companies, or system integrators.