Changeset 38 for anr/section-2.tex


Ignore:
Timestamp:
Jan 19, 2010, 11:01:35 AM (14 years ago)
Author:
coach
Message:
 
File:
1 edited

Legend:

Unmodified
Added
Removed

  • anr/section-2.tex

    r32 r38  
    66complexity of design problems. Such methods, addressing these challenges starting from high levels of
    77abstraction, will have to perform large solution space explorations both for software and (possibly
    8 reconfigurable) hrdware, involving almost marginal design effort and offering a high predictability of results
    9 with respect to cost- and performance- objectives.
     8reconfigurable) hardware, reducing the design effort and offering a high predictability of results
     9with respect to cost and performance objectives.
    1010Current design methodologies provide quite low-level abstraction capabilities. However in a few years
    1111from now tens of programmable processors will be embedded in an IC with more than 100M
    12 transistors adding to the complexity of the problem of designing such systems. Taking into account
    13 that the complexity of the software part is increasing at an even faster rate, current solutions for
    14 design space exploration, mainly manually based, by no means do supply an adequate performance.
     12transistors, therefore adding to the complexity of the problem of designing such systems.
     13Taking into account that the complexity of the software part is increasing at an even
     14faster rate, current solutions for design space exploration, mainly manually based, by no
     15means do supply an adequate efficiency.
    1516Consequently, there is an urgent need to leverage system level
    1617exploration through the use of a high level specification of the application and an early design
    … …  
    2223\\
    2324Thus, new system-level design flows need to be developed, enabling the exploration of an application
    24 independently of the implementation, almost at the beginning of the design process. A
    25 fundamental element of this evolution is the definition of abstraction layers that should allow the
    26 systematic re-use of software and hardware components at the system level driven by performance estimation
    27 and analysis. In this context, COACH will combine modeling and estimation methods and
    28 compilers and design space exploration techniques. This approach will cause a real breakthrough in
    29 the embedded system design methodology, i.e. one of the radical innovations.
     25independently of the implementation, almost at the beginning of the design process.
     26A fundamental element of this evolution is the definition of abstraction layers that should allow the
     27performance driven re-use of software and hardware components at the system level.
     28In this context, COACH will combine modeling and estimation methods and compilers and
     29design space exploration techniques. This approach will be a radical innovation in
     30embedded system design methodology.
    3031\\
    31 The reason is that COACH precedes the use of high-level design tools in the embedded
    32 systems design flows. In that way, it will make possible a real and efficiently combined
    33 exploitation of high-level synthesis tools, parallelising approaches and compilers, already
     32The reason is that the COACH framework is applied before high-level design tools in the embedded
     33systems design flow. In that way, it will make possible a real and efficiently combined
     34exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
    3435available on the market. These tools and approaches are not yet massively adopted, precisely
    35 because this decisive design step is missing. COACH will indeed permit (i) to predict and
     36because this preliminary design step is missing. COACH will indeed permit (i) to predict and
    3637control implementation optimizations, (ii) to target multiple implementation technologies
    3738(and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
    … …  
    4344a lower global cost.
    4445\par
    45 To get an efficient embedded system, designer has to take into account
    46 application characteristics when it chooses one of the former technologies.
    47 This choice is not easy and in most cases designer has to try different
     46To get an efficient embedded system, the system designer has to take into account
     47application characteristics when it chooses one of the available technologies.
     48This choice is not easy and in most cases the designer has to try different
    4849technologies to retain the most adapted one.
    4950\\
    5051The first objective of COACH is to provide an open-source framework to
    51 design embedded system on FPGA device.
    52 COACH framework allows designer to explore various software/hardware
     52design embedded system on FPGA devices.
     53The COACH framework allows the designer to explore various software/hardware
    5354partitions of the target application, to run timing and functional
    5455simulations and to generate automatically both the software and the
    … …  
    6566Micro-architectural exploration: When hardware components are required, the
    6667HLS tools of the framework generate them automatically. At this stage the
    67 framework provides various HLS tools allowing the micro-architectural space
     68framework provides various HLS tools that allow the micro-architectural space
    6869design exploration. The exploration criteria also are throughput, latency
    6970and power consumption.
    … …  
    7475
    7576\item
    76 Performance measurement: For each point of design space exploration,
    77 metrics of criteria are available such as throughput, latency, power
     77Performance measurement: For each point in the design space,
     78figures of merit are available such as throughput, latency, power
    7879consumption, area, memory allocation and data locality. They are evaluated
    79 using virtual prototyping, estimation or analysing methodologies.
     80using virtual prototyping, estimation or analyzing methodologies.
    8081\item
    81 Targeted hardware technology: The COACH description of system is
    82 independent of the FPGA family.  Every point of the design exploration
     82Targeted hardware technology: The COACH description of a system is
     83independent of the FPGA family.  Every point of the design
    8384space can be implemented on any FPGA having the required resources.
    8485Basically, COACH handles both Altera and Xilinx FPGA families.
    … …  
    8687As an extension of embedded system design, COACH deals also with High
    8788Performance Computing (HPC).
    88 In HPC, the kind of targeted application is an existing one running on PC.
    89 COACH helps designer to accelerate it by migrating critical parts into a
    90 SoC implemented on a FPGA plugged to the PC bus.
     89In HPC, the kind of targeted application is an existing one running on a PC.
     90The COACH framework helps designer to accelerate it by migrating critical parts into a
     91SoC implemented on an FPGA plugged to the PC bus.
    9192\par
    92 COACH is the result of the will of several laboratory to unify their know
    93 how and skills in the following domains: Operating system and hardware
    94 communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
    95 HLS (LIP6, Lab-STIC and LIP).
     93COACH is the result of the will of several laboratories to unify their knowhow
     94and skills in the following domains: Operating system and hardware
     95communication (\tima, \citi), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
     96HLS (\upmc, \ubs) and compilation (\irisa, \lip).
    9697The project objective is to integrate these various domains into a unique
    9798free framework (licence ...) masking as much as possible these domains and
Note: See TracChangeset for help on using the changeset viewer.