Changeset 47 for anr/task-2.tex

Timestamp:

Jan 29, 2010, 2:31:27 PM (14 years ago)

Author:

coach

Message:

modifs USB

File:

• anr/task-2.tex (modified) (2 diffs)

anr/task-2.tex

@@ -69 +69 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgAlteraSystemC);
+    \item{V1}{6}{12}{d}{\Subs}{UBS architecture}
+\mustbecompleted{FIXME:UBS ARGH!!!!!\\
+    1) Attention si vous touchez au MWMR, ils y a 3 composants MWMR. \\
+    2) UBS architecture} est tres mal choisit, ca fait un 4ieme template
+}
+       \setMacroInAuxFile{gautMWMRoptimization}
+       Specification of an optimized MWMR component to handle data interleaving (space and time).
+       This evolution aims to solve out of order communication weakness of the classical MWMR. 
+    \item{V2}{12}{24}{x}{\Subs}{UBS architecture}
+       Release of the tool that generates the VHDL description of the optimized MWMR component
+       and its corresponding SystemC module. 
+    \item{VF}{24}{30}{x}{\Subs}{UBS architecture}
+       Final release of the tool that generates the VHDL description of the optimized MWMR component
+       and its corresponding SystemC module (\gautMWMRoptimization).
     \end{livrable}
 \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
@@ -91 +105 @@
         Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     \end{livrable}
-% moved in task 1
-%\item This \ST relies to definition and implementation of the enhanced communication
-%    schemes usable in the definition of communicante task graph.
-%    \begin{livrable}
-%    \item{}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
-%        graph inputs (task graph, task description, communication schemes). 
-%    \end{livrable}
-%\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera
-%    architectural template.
-%    \begin{livrable}
-%    \item{}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
-%        SystemC model of the MWMR with a PLB bus interface.
-%    \item{}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
-%        SystemC model of the MWMR with an AVALON bus interface.
-%    \end{livrable}
-% FIXME:CITI
 \end{workpackage}