Changeset 49 for anr/section-1.tex
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anr/section-1.tex
r31 r49 1 1 % les objectifs globaux, 2 During the last decades, the design of complex digital systems is more and more reserved to the 3 high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs 4 due to increasing NRE (Non Recurring-Engineering) costs. The market of digital systems is about 5 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. 6 Digital system design has been investigated since the eighties for Application 7 Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP) and parallel computing on 8 multiprocessor machines or networks. Other technologies appeared like Very Large 9 Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP). 10 Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies 11 and thus requieres the design of System-on-Chip (SoC) and Multi-Processors SoC (MPSoC). 12 Nowadays, Field Programmable Gate Arrays (FPGA), such as the Virtex5 from Xilinx 13 or the Stratix4 from Altera, can implement a complete SoC with multiple processors and 14 several coprocessors for less than 10K euros per device. 15 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 16 Co-design, High-Level Synthesis...) is now mature and allow the automation of the design of digital 17 systems and drastically decrease their cost in terms of manpower. 18 Thus, coupling both FPGA and ESL methodologies will soon allow small and medium 19 enterprises (SMEs) and major companies to get into new, low and medium volume markets, 20 to design highly innovative devices and to prototype complete digital systems. 21 \par 22 The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of 23 complex digital systems on FPGA devices. A digital system is an application integrated into one or 24 several chips. These chips can be embedded in devices such as a personal digital assistant (PDA), 25 an ambiant computing component or a wireless sensor network (WSN). They can also be used on a board connected 26 to a PC to accelerate an application as in High-Performance Computing (HPC) or in High-Speed Signal 27 Processing (HSSP). 28 29 COACH will reduce the NRE costs to the design costs (the FPGA device being only a few 30 K\euro) and drastically reduces them. If proper tools, better suited to 31 softaware developers are created, one 32 can expect that FPGA based devices 33 will gain market share over Multi-core CPUs and GPUs HPC based solutions. 34 Moreover this market can also be boosted by small and even very small new companies 35 that will be able to propose embedded system and accelerating solutions for standard 36 software applications with acceptable prices.\\ 37 38 The main idea is to increase the design productivity by selecting a given flexible architectural template 39 and targeting the area of complex digital systems. This project involves the development of methodologies and 40 tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC) 41 of whole systems, while taking into account different application constraints (power consumption, throughput, latency...). 42 The project will also optimize an 43 important interface, usually not taken into account, between the high-level synthesis and the implementation 44 techniques on physical targets and the associated low level tools (logic synthesis and compilation). 45 The design flow will allow, from a high-level specification (written in the C language), to estimate, analyze, optimize the 46 performances and then implement a real architecture. The COACH framework will allow the designer to explore various 47 software/hardware partitioning scenario for the target application through timing and functional simulations and to 48 generate automatically both the software and the synthesizable description of the hardware. 2 The market of digital systems is about 4,600 M$ today and is estimated to 3 5,600 M$ in 2012. But the ever growing applications complexity involves 4 higher integration of heterogeneous technologies and requires the design of 5 complex Multi-Processors System on Chip (MPSoC). 6 During the last decade, the design of complex digital ASICs (Application Specific 7 Integrated Circuits) appeared to be more and more reserved to high volume markets, because 8 the design and fabrication costs of such components exploded, due to increasing NRE (Non 9 Recurring-Engineering) costs. 10 \\ 11 FPGA (Field Programmable Gate Array) components, such as the 12 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays 13 implement a complete MPSoC with multiple processors and several 14 coprocessors for few keuros per device. 15 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 16 Co-design, High-Level Synthesis...) are now mature and allow the automation of 17 a system level design flow that targets FPGA devices. 18 We believe that coupling FPGA technologies and ESL methodologies 19 will allow both SMEs (Small and Medium Enterprise) and 20 major companies to design innovative devices and to enter new, low and 21 medium volume markets. 22 \\ 23 The objective of COACH is to provide an integrated design flow, based on the 24 SoCLib infrastructure~\cite{soclib}, and optimized for the design of 25 multi-processors digital systems targetting FPGA devices. 26 Such digital system are generally integrated 27 into one or several chips, and there is two types of applications: 28 It can be embedded (autonomous) applications 29 such as personal digital assistants (PDA), ambiant computing components 30 or wireless sensor networks (WSN) 31 They can also be extension boards connected to a PC to accelerate a specific computation, 32 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). 33 \\ 34 The COACH project fundamental issues are related to design methodologies 35 for digital systems, providing estimation, exploration and design tools 36 targeting both performance and power optimization at all the abstraction 37 levels of the flow (system, architecture, algorithm and logic). 49 38 50 39 %verrous scientifiques et techniques 51 The main contributions of the project are: 52 \begin{itemize} 53 \item Targeted hardware architecture and technology: 54 COACH will handle both Altera and Xilinx FPGA technologies. COACH will define 55 architectural templates that can be customized by additional dedicated coprocessors and ASIPs. 56 The parameters of the architectural templates will be the number of CPU, the operating system... 57 %the coprocessors, the number and the size of the FIFO communication channels 58 Basically, the 3 following architectural templates will be provided: 59 \begin{itemize} 60 \item A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus, 61 \item An Altera architectural template based on the NIOS and the AVALON bus, 62 %FIXME 63 % The following point has to be confirmed by XILINX 64 % Microblaze+OPB => ARM+Amba ??? 65 \item A Xilinx architectural template based on the MICROBLAZE and the OPB bus. 66 \end{itemize} 67 Moreover, the specification of the application will be independant of both the template 68 architecture and the selected technology. 69 \item Design space exploration: The COACH environment will allow the selection and parametrization of 70 the target architecture, the definition of the hardware/software partitioning and the profiling of the application. 71 For each point in the design space, metrics such as throughput, latency, power consumption, 72 silicon area, memory allocation and data locality will be provided. 73 This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies. 74 \item Hardware accelerators synthesis (HAS): COACH will allow the automatic generation of hardware accelerators 75 when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and 76 source-level transformations (loop transformations and memory optimisation) will be provided. 77 This will allow further exploration of the micro-architectural design space. 78 HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs. 79 data dominated). The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer. 80 \item Communication interface: Coach will define and implement HW/SW communication management and define APIs 81 enabling communication between processors, processor/coprocessors, FPGA and PC. 82 \end{itemize} 83 %In HPC, the kind of targeted application is an existing one running on PC. 84 %COACH helps designer to accelerate it by migrating critical parts into a 85 %SoC implemented on a FPGA plugged to the PC bus.\\ 86 %FIXME licence a speficier 87 88 The COACH tools will be designed to hide the hardware as much as possible from the end user. 89 It will thus be mainly dedicated to system designers. 90 91 40 \vspace*{.9ex}\par 41 The COACH environment mixes and integrates several hardware and software technologies. 42 The more important technologies are: 43 \begin{description} 44 \item[Design space exploration] 45 The COACH environment will support design space exploration to help the 46 system designer to select and parameterize the target architecture, and to 47 define the proper hardware/software partitioning of the application. 48 For each point in the design space, metrics such as throughput, latency, power 49 consumption, silicon area, memory allocation and data locality will be provided. 50 These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure 51 and high-level estimation methodologies. 52 \item[Hardware accelerators synthesis (HAS)] 53 COACH will allow the automatic generation of hardware accelerators when required. 54 Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor 55 (ASIP) design environment and source-level transformation tools (loop transformations 56 and memory optimisation) will be provided. 57 This will allow further exploration of the micro-architectural design space. 58 HLS tools are sensitive to the coding style of the input specification and the domain 59 they target (control vs. data dominated). 60 The HLS tools of COACH will support a common language and coding style to avoid 61 re-engineering by the designer. 62 \item[Targeted hardware architecture and technology] 63 COACH will handle both \altera and \xilinx FPGA devives. 64 COACH will define architectural templates that can be customized by adding 65 dedicated coprocessors and ASIPs and by fixing template parameters such as 66 the number of CPU and the operating system. 67 Basically, the 3 following architectural templates will be provided: 68 \begin{enumerate} 69 \item A Neutral architectural template based on the SoCLib IP core library and the 70 VCI/OCP communication infrastructure. 71 \item An \altera architectural template based on the \altera IP core library and the 72 AVALON system bus. 73 \item A \xilinx architectural template based on the Xlinx IP core library and the OPB 74 system bus. 75 \end{enumerate} 76 Moreover, the specification of the application will be independant of both the 77 architectural template and the target FPGA device. 78 \item[Communication interfaces] 79 Coach will define and implement an homogeneous HW/SW communication infrastructure and 80 communication APIs (Application Programming Interface). 81 These laters are on chip communications between processors and coprocessors, 82 and external communications between the FPGA and the host PC. 83 \end{description} 84 The COACH design flow will be dedicated to system designers, and will as 85 much as possible hide the hardware characteristics to the end user. 86 %From the end user point of view, the specification of the application will be 87 %independant from both the architectural template and from the selected FPGA 88 %family. 92 89 93 90 % le programme de travail 94 91 \vspace*{.9ex}\par 92 %The COACH project targets fundamental issues related to design methodologies for 93 %digital systems by providing estimation, exploration and design tools targeting both 94 %performance and power optimization at all the abstraction levels of the flow (system, 95 %architecture, algorithm and logic). 96 To reach this ambitious goal, the project will rely on the experience and the 97 complementariness of partners in the following domains: 98 Operating system and communication middleware (\tima, \upmc), 99 MPSoC architectures (\tima, \ubs, \upmc), 100 ASIP architectures (\irisa), 101 High Level Synthesis (\tima, \ubs, \upmc) and loop tranformations (\lip). 102 \\ 103 %The CoACH proposal can be described as an extension of the SoCLib virtual 104 %prototyping platform to the FPGA technologies. 105 The COACH project does not start from scratch. 106 It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping, 107 (DSX, component library), operating systems (MutekH, DNA/OS). 108 It also leverages on several existing technologies: 109 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 110 on the ROMA~\cite{roma} project for ASIP, 111 an the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for loop tranformations, 112 and on the \xilinx and \altera IP core libraries. 113 Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration 114 bitstreams. 115 \par 116 The COACH proposal has been prepared during one year by a technical working group 117 involving all the academic partners (one monthly meeting from january 2009 to february 118 2010). The objective of these meetings was to analyse the issues of integrating 119 and enhancing the formers tools and tecnnologies into a unique framework allowing to both 120 virtual prototyping and hardware generation. 121 Because the SocLib platform is the base of this project, it may be described as an 122 extension of the SoCLib platform. 123 \par 124 The main development of the COACH project steps are: 125 \begin{enumerate} 126 \item Definition of the end user inputs: 127 The coarse grain parallelism of the application will be described as a communicating 128 task graph, each task being described in C language. 129 Similarly the architectural templates with their parameters and the design constraints 130 will be specified. 131 \item Definition of an internal format for representing task. 132 \item Development of the GCC pluggin for generating the internal format of a 133 C task. 134 \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write 135 the internal format. This will allow to swap from one tool to another one, and to 136 chain them if necessary. 137 \item Modication of the DSX tool (Design Space eXplorer) of the SocLib 138 platform to generate the bitstream for the various FPGA families and architectural 139 templates. 140 \item Development of new tools such as ASIP compiler, HPC design environment and 141 dynamic reconfiguration of FPGA devices. 142 \end{enumerate} 143 \par 144 The two major FPGA companies \altera and \xilinx are participating to this 145 project to support the partners providing the software technologies, and to 146 help to generate efficient bitsream for both FPGA families. 147 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide 148 real use cases to benchmark the COACH design environment. 149 \par 150 Following the general policy of the SoCLib platform, the COACH project will be an open 151 infrastructure, available in the framework of the SoCLib server. 152 The architectural templates, and the COACH software tools will be distributed under the 153 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib 154 IP core library) will be freely available for non commercial use. Commercial licences 155 will be negociated for industrial exploitation. 95 156 96 The COACH project targets fundamental issues related to design methodologies for97 digital systems by providing estimation, exploration and design tools targeting both98 performance and power optimization at all the abstraction levels of the flow (system,99 architecture, algorithm and logic).100 101 To reach this ambitious aim, this project will lean on the experience and the complementariness102 of partners in the following domains: Operating system and hardware103 communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and104 HLS (LIP6 and Lab-STICC) and loop tranformations (LIP).105 COACH does not start from scratch but relies106 on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for107 SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on108 ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.109 110 The project objective is to enhance and seamlessly integrate these tools into111 a unique open source framework.112 The main steps of this project are:113 1) Definition of the user inputs: application description as set of communicating tasks, each114 task beeing described in the C++ language; architectural template with its parameters; design constraints.115 2) Definition of the internal \xcoach format for representing a task.116 3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.117 4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to118 swap from one tool to another one and to chain them.119 5) Modification of the Design System eXplorator (DSX) of the SocLib platform to let the user120 explore the design space and then to generate the bitstream.121 %FIXME : a completer122 \par123 124 The two major FPGA companies Altera and Xilinx expect this by supporting125 and participating in this project.126 The role of the industrial partners BULL, THALES, XXX is to provide real127 benchmarks to guide the design of the framework and to prove that COACH is128 usuable and cover a large spectrum of applications.129 130 The COACH arhitectural templates will be freely distributed for non commercial use.131 The software tools of COACH will be developped under the General Public Licence.132
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