Changeset 49


Ignore:
Timestamp:
Jan 30, 2010, 8:35:33 PM (14 years ago)
Author:
coach
Message:

IA: 1) updated section 1. 2) Updated task 0 6 7. 3) enhanced delivery table printing.

Location:
anr
Files:
7 edited

Legend:

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  • anr/anr.sty

    r36 r49  
    3232\let\ALL\disable%
    3333\let\IRISA\disable%
    34 \let\CITI\disable%
    3534\let\LIP\disable%
    3635\let\TIMA\disable%
    … …  
    4140\let\BULL\disable%
    4241\let\THALES\disable%
     42\let\NAVTEL\disable%
    4343\let\ZIED\disable%
    4444}{%
    4545\ifx\ALL\enable%
    4646  \ifx\IRISA\disable\let\IRISA\enable\fi%
    47   \ifx\CITI\disable\let\CITI\enable\fi%
    4847  \ifx\LIP\disable\let\LIP\enable\fi%
    4948  \ifx\UPMC\disable\let\UPMC\enable\fi%
    … …  
    5453  \ifx\BULL\disable\let\BULL\enable\fi%
    5554  \ifx\THALES\disable\let\THALES\enable\fi%
     55  \ifx\NAVTEL\disable\let\NAVTEL\enable\fi%
    5656  \ifx\ZIED\disable\let\ZIED\enable\fi%
    5757\fi%
    … …  
    5959\def\@partner{\begin{small}\textcolor{blue}{part.}\end{small}}
    6060\def\@IRISA{\ifx\IRISA\disable{}\else\ifx\IRISA\enable{\@partner}\else{\@leader}\fi\fi}%
    61 \def\@CITI{\ifx\CITI\disable{}\else\ifx\CITI\enable{\@partner}\else{\@leader}\fi\fi}%
    6261\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{\@partner}\else{\@leader}\fi\fi}%
    6362\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{\@partner}\else{\@leader}\fi\fi}%
    … …  
    6867\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{\@partner}\else{\@leader}\fi\fi}%
    6968\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{\@partner}\else{\@leader}\fi\fi}%
     69\def\@NAVTEL{\ifx\NAVTEL\disable{}\else\ifx\NAVTEL\enable{\@partner}\else{\@leader}\fi\fi}%
    7070\def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{\@partner}\else{\@leader}\fi\fi}%
    7171\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|}\hline
    72 \Sirisa  & \Sciti  & \Slip  & \Stima  & \Subs  & \Supmc  & \Saltera & \Sxilinx & \Sbull  & \Sthales & \Szied \\\hline
    73 \@IRISA  & \@CITI  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@ALTERA & \@XILINX & \@BULL  & \@THALES & \@ZIED \\\hline
     72\Sirisa  & \Slip  & \Stima  & \Subs  & \Supmc  & \Saltera & \Sxilinx & \Sbull  & \Sthales & \Snavtel & \Szied \\\hline
     73\@IRISA  & \@LIP  & \@TIMA  & \@UBS  & \@UPMC  & \@ALTERA & \@XILINX & \@BULL  & \@THALES & \@NAVTEL & \@ZIED \\\hline
    7474\end{tabular}\par
    7575}
    … …  
    9999\newenvironment{livrable}%
    100100{%
     101 \newif\ifLivrableTopLine\LivrableTopLinetrue
     102 \newif\ifLivrableStart\LivrableStarttrue
     103 \def\livrableTableDef{\begin{tabular}{|c|c|c|c|p{.625\linewidth}|}\hline}
     104 \def\livrableTableLine##1##2##3##4{%
     105    \makebox[3.5em]{\begin{small}##1\end{small}} &
     106    \makebox[2.2em]{\begin{small}##2\end{small}} &
     107    \makebox[1.5em]{\begin{small}##3\end{small}} &
     108    \makebox[2.2em]{\begin{small}##4\end{small}} &
     109 }
     110 \def\livrableTableTopLine{%
     111   \livrableTableLine{number}{date}{type}{resp.} description
     112 }
    101113 \livrablecnt-1
    102  \ifvmode\else\\\fi
     114 \ifvmode\else\vspace{.75ex}\\\fi
    103115 \def\item##1##2##3##4##5##6{%
    104116        \def\tmpa{##1}\def\vers{}
    105         \def\tmp{}  \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{VF}\fi%
    106     \def\tmp{1} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi%
    107     \def\tmp{V1}\ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\fi%
     117        \def\tmp{}  \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{VF}\global\LivrableStarttrue\fi%
     118    \def\tmp{1} \ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\global\LivrableStarttrue\fi%
     119    \def\tmp{V1}\ifx\tmp\tmpa\global\advance\livrablecnt1\def\vers{V1}\global\LivrableStarttrue\fi%
    108120    \def\tmp{2} \ifx\tmp\tmpa\def\vers{V2}\fi%
    109121    \def\tmp{V2}\ifx\tmp\tmpa\def\vers{V2}\fi%
    … …  
    117129      \let\xcoach\relax
    118130      \let\xcoachplus\relax
    119       \let\xilinx\relax
    120       \let\altera\relax
     131      \let\irisa\relax    \let\Sirisa\relax
     132      \let\lip\relax      \let\Slip\relax
     133      \let\tima\relax     \let\Stima\relax
     134      \let\ubs\relax      \let\Subs\relax
     135      \let\upmc\relax     \let\Supmc\relax
     136      \let\altera\relax   \let\Saltera\relax
     137      \let\xilinx\relax   \let\Sxilinx\relax
     138      \let\bull\relax     \let\Sbull\relax
     139      \let\thales\relax   \let\Sthales\relax
     140      \let\zied\relaxe    \let\Szied\relax
     141      \let\navtel\relax   \let\Snavtel\relax
    121142      \immediate\write\ganttdata{%
    122143        T=\the\taskcnt\space S=\the\subtaskcnt\space%
    … …  
    125146    }
    126147    \\\hline
    127     \begin{small}\textsc{\name}\end{small} &
    128     \begin{small}\textsc{T0+##3}\end{small} &
    129     \begin{small}\textsc{##4}\end{small} &
    130     \begin{small}\textsc{##5}\end{small} &
     148    \ifLivrableTopLine
     149      \ifLivrableStart\hline\hline\fi
     150    \else
     151      \ifLivrableStart\end{tabular}\\\livrableTableDef\fi
     152    \fi
     153    \global\LivrableTopLinefalse
     154    \global\LivrableStartfalse
     155    \livrableTableLine%
     156        {\textsc{\name}}%
     157        {\textsc{T0+##3}}%
     158        {\textsc{##4}}%
     159        {\textsc{##5}}%
    131160 }
    132161% \begin{small}
    133  \begin{tabular}{|c|c|c|c|p{.55\linewidth}|}\hline%
    134  \makebox[5em]{number} & \makebox[3em]{date} & type & resp. & description
     162 \livrableTableDef
     163 \livrableTableTopLine
     164 %\begin{tabular}{|c|c|c|c|p{.55\linewidth}|}\hline%
     165 %\makebox[3.5em]{number} & \makebox[1.5em]{date} & type & resp. & description
    135166}
    136 {\\\hline\end{tabular}%
     167{\\\hline\end{tabular}\\%
    137168%\end{small}\\%
    138169}

  • anr/anr.tex

    r46 r49  
    3333%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    3434\def\Sformat#1{\begin{small}\textsc{#1}\end{small}}
    35 \def\irisa{IRISA\xspace}    \def\Sirisa{\Sformat{IRI}\xspace}
    36 \def\citi{CITI\xspace}      \def\Sciti{\Sformat{CITI}\xspace}
    37 \def\lip{LIP\xspace}        \def\Slip{\Sformat{LIP}\xspace}
    38 \def\tima{TIMA\xspace}      \def\Stima{\Sformat{TIMA}\xspace}
    39 \def\ubs{UBS\xspace}        \def\Subs{\Sformat{UBS}\xspace}
    40 \def\upmc{LIP6\xspace}      \def\Supmc{\Sformat{LIP6}\xspace}
    41 \def\altera{ALTERA\xspace}  \def\Saltera{\Sformat{ALTE}\xspace}
    42 \def\xilinx{XILINX\xspace}  \def\Sxilinx{\Sformat{XILX}\xspace}
    43 \def\bull{BULL\xspace}      \def\Sbull{\Sformat{BULL}\xspace}
    44 \def\thales{THALES\xspace}  \def\Sthales{\Sformat{THAL}\xspace}
    45 \def\zied{FLEXRAS\xspace}   \def\Szied{\Sformat{FLEX}\xspace}
    46 \def\navtel{NAVTEL System\xspace}   \def\Szied{\Sformat{NAV}\xspace}
     35\def\irisa{IRISA\xspace}          \def\Sirisa{\Sformat{IRI}\xspace}
     36\def\citi{CITI\xspace}            \def\Sciti{\Sformat{CITI}\xspace}
     37\def\lip{LIP\xspace}              \def\Slip{\Sformat{LIP}\xspace}
     38\def\tima{TIMA\xspace}            \def\Stima{\Sformat{TIMA}\xspace}
     39\def\ubs{UBS\xspace}              \def\Subs{\Sformat{UBS}\xspace}
     40\def\upmc{LIP6\xspace}            \def\Supmc{\Sformat{LIP6}\xspace}
     41\def\altera{ALTERA\xspace}        \def\Saltera{\Sformat{ALTE}\xspace}
     42\def\xilinx{XILINX\xspace}        \def\Sxilinx{\Sformat{XILX}\xspace}
     43\def\bull{BULL\xspace}            \def\Sbull{\Sformat{BULL}\xspace}
     44\def\thales{THALES\xspace}        \def\Sthales{\Sformat{THAL}\xspace}
     45\def\zied{FLEXRAS\xspace}         \def\Szied{\Sformat{FLEX}\xspace}
     46\def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace}
    4747
    4848\def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
    … …  
    203203\end{itemize}}
    204204
    205 \subsubsection{Task 0: \textit{Project Managment}}
     205\subsubsection{Task 0: \textit{Project Management}}
    206206\input{task-0}
    207207
    208 \subsubsection{Task 1: \textit{\backbone}}
     208\subsubsection{Task 1: \textit{\Backbone}}
    209209\input{task-1}
    210210
    211 \subsubsection{Task 2: \textit{system generation}}
     211\subsubsection{Task 2: \textit{System generation}}
    212212\input{task-2}
    213213
    … …  
    223223\subsubsection{Task 6: \textit{Industrial Demonstrators}}
    224224\input{task-6}
     225
     226\subsubsection{Task 8: \textit{Dissemination}}
     227\input{task-7}
    225228
    226229\subsection{Tasks schedule, deliverables and milestones}

  • anr/section-1.tex

    r31 r49  
    11% les objectifs globaux,
    2 During the last decades, the design of complex digital systems is more and more reserved to the
    3 high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs
    4 due to increasing NRE (Non Recurring-Engineering) costs. The market of digital systems is about
    5 4,600 M\$ today and is estimated to 5,600 M\$ in 2012.
    6 Digital system design has been investigated since the eighties for Application
    7 Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP) and parallel computing on
    8 multiprocessor machines or networks.  Other technologies appeared like Very Large
    9 Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP).
    10 Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies
    11 and thus requieres the design of System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
    12 Nowadays, Field Programmable Gate Arrays (FPGA), such as the Virtex5 from Xilinx
    13 or the Stratix4 from Altera, can implement a complete SoC with multiple processors and
    14 several coprocessors for less than 10K euros per device.
    15 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
    16 Co-design, High-Level Synthesis...) is now mature and allow the automation of the design of digital
    17 systems and drastically decrease their cost in terms of manpower.
    18 Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
    19 enterprises (SMEs) and major companies to get into new, low and medium volume markets,
    20 to design highly innovative devices and to prototype complete digital systems.
    21 \par
    22 The objective of COACH is to provide a consolidated flow, integrated and optimized for the design of
    23 complex digital systems on FPGA devices.  A digital system is an application integrated into one or
    24 several chips. These chips can be embedded in devices such as a personal digital assistant (PDA),
    25 an ambiant computing component or a wireless sensor network (WSN). They can also be used on a board connected
    26 to a PC to accelerate an application as in High-Performance Computing (HPC) or in High-Speed Signal
    27 Processing (HSSP).
    28 
    29 COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
    30 K\euro) and drastically reduces them. If proper tools, better suited to
    31 softaware developers are created, one
    32 can expect that FPGA based devices
    33 will gain market share over Multi-core CPUs and GPUs HPC based solutions.
    34 Moreover this market can also be boosted by small and even very small new companies
    35 that will be able to propose embedded system and accelerating solutions for standard
    36 software applications with acceptable prices.\\
    37 
    38 The main idea is to increase the design productivity by selecting a given flexible architectural template
    39 and targeting the area of complex digital systems. This project involves the development of methodologies and
    40 tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC)
    41 of whole systems, while taking into account different application constraints (power consumption, throughput, latency...).
    42 The project will also optimize an
    43 important interface, usually not taken into account, between the high-level synthesis and the implementation
    44 techniques on physical targets and the associated low level tools (logic synthesis and compilation).
    45 The design flow will allow, from a high-level specification (written in the C language), to estimate, analyze, optimize the
    46 performances and then implement a real architecture. The COACH framework will allow the designer to explore various
    47 software/hardware partitioning scenario for the target application through timing and functional simulations and to
    48 generate automatically both the software and the synthesizable description of the hardware.
     2The market of digital systems is about 4,600 M$ today and is estimated to
     35,600 M$ in 2012. But the ever growing applications complexity involves
     4higher integration of heterogeneous technologies and requires the design of
     5complex Multi-Processors System on Chip (MPSoC).
     6During the last decade, the design of complex digital ASICs (Application Specific
     7Integrated Circuits) appeared to be more and more reserved to high volume markets, because
     8the design and fabrication costs of such components exploded, due to increasing NRE (Non
     9Recurring-Engineering) costs.
     10\\
     11FPGA (Field Programmable Gate Array) components, such as the
     12Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
     13implement a complete MPSoC with multiple processors and several
     14coprocessors for few keuros per device.
     15In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     16Co-design, High-Level Synthesis...) are now mature and allow the automation of
     17a system level design flow that targets FPGA devices.
     18We believe that coupling FPGA technologies and ESL methodologies
     19will allow both SMEs (Small and Medium Enterprise) and
     20major companies to design innovative devices and to enter new, low and
     21medium volume markets.
     22\\
     23The objective of COACH is to provide an integrated design flow, based on the
     24SoCLib infrastructure~\cite{soclib}, and optimized for the design of
     25multi-processors digital systems targetting FPGA devices.
     26Such digital system are generally integrated
     27into one or several chips, and there is two types of applications:
     28It can be embedded (autonomous) applications
     29such as personal digital assistants (PDA), ambiant computing components
     30or wireless sensor networks (WSN)
     31They can also be extension boards connected to a PC to accelerate a specific computation,
     32as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
     33\\
     34The COACH project fundamental issues are related to design methodologies
     35for digital systems, providing estimation, exploration and design tools
     36targeting both performance and power optimization at all the abstraction
     37levels of the flow (system, architecture, algorithm and logic).
    4938
    5039%verrous scientifiques et techniques
    51 The main contributions of the project are:
    52 \begin{itemize}
    53 \item Targeted hardware architecture and technology:
    54 COACH will handle both Altera and Xilinx FPGA technologies. COACH will define
    55 architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
    56 The parameters of the architectural templates will be the number of CPU, the operating  system... 
    57 %the coprocessors, the number and the size of the FIFO communication channels
    58 Basically, the 3 following architectural templates will be provided:
    59 \begin{itemize}
    60 \item A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
    61 \item An Altera architectural template based on the NIOS and the AVALON bus,
    62 %FIXME
    63 % The following point has to be confirmed by XILINX
    64 % Microblaze+OPB => ARM+Amba ???
    65 \item A Xilinx architectural template based on the MICROBLAZE and the OPB bus.
    66 \end{itemize}
    67 Moreover, the specification of the application will be independant of both the template
    68 architecture and the selected technology.
    69 \item Design space exploration: The COACH environment will allow the selection and parametrization of
    70 the target architecture, the definition of the hardware/software partitioning and the profiling of the application.
    71 For each point in the design space, metrics such as throughput, latency, power consumption,
    72 silicon area, memory allocation and data locality will be provided.
    73 This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
    74 \item Hardware accelerators synthesis (HAS): COACH will allow the automatic generation of hardware accelerators
    75 when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and
    76 source-level transformations (loop transformations and memory optimisation) will be provided.
    77 This will allow further exploration of the micro-architectural design space.
    78 HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs.
    79 data dominated). The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer.
    80 \item Communication interface: Coach will define and implement HW/SW communication management and define APIs
    81 enabling communication between processors, processor/coprocessors,  FPGA and PC.
    82 \end{itemize}
    83 %In HPC, the kind of targeted application is an existing one running on PC.
    84 %COACH helps designer to accelerate it by migrating critical parts into a
    85 %SoC implemented on a FPGA plugged to the PC bus.\\
    86 %FIXME licence a speficier
    87 
    88 The COACH tools will be designed to hide the hardware as much as possible from the end user.
    89 It will thus be mainly dedicated to system designers.
    90 
    91 
     40\vspace*{.9ex}\par
     41The COACH environment mixes and integrates several hardware and software technologies.
     42The more important technologies are:
     43\begin{description}
     44\item[Design space exploration]
     45    The COACH environment will support design space exploration to help the
     46    system designer to select and parameterize the target architecture, and to
     47    define the proper hardware/software partitioning of the application.
     48    For each point in the design space, metrics such as throughput, latency, power
     49    consumption, silicon area, memory allocation and data locality will be provided.
     50    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
     51    and high-level estimation methodologies.
     52\item[Hardware accelerators synthesis (HAS)]
     53    COACH will allow the automatic generation of hardware accelerators when required.
     54    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
     55    (ASIP) design environment and source-level transformation tools (loop transformations
     56    and memory optimisation) will be provided.
     57    This will allow further exploration of the micro-architectural design space.
     58    HLS tools are sensitive to the coding style of the input specification and the domain
     59    they target (control vs. data dominated).
     60    The HLS tools of COACH will support a common language and coding style to avoid
     61    re-engineering by the designer.
     62\item[Targeted hardware architecture and technology]
     63    COACH will handle both \altera and \xilinx FPGA devives.
     64    COACH will define architectural templates that can be customized by adding
     65    dedicated coprocessors and ASIPs and by fixing template parameters such as
     66    the number of CPU and the operating system.
     67    Basically, the 3 following architectural templates will be provided:
     68    \begin{enumerate}
     69    \item A Neutral architectural template based on the SoCLib IP core library and the
     70      VCI/OCP communication infrastructure.
     71    \item An \altera architectural template based on the \altera IP core library and the
     72      AVALON system bus.
     73    \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
     74      system bus.
     75    \end{enumerate}
     76    Moreover, the specification of the application will be independant of both the
     77    architectural template and the target FPGA device.
     78\item[Communication interfaces]
     79    Coach will define and implement an homogeneous HW/SW communication infrastructure and
     80    communication APIs (Application Programming Interface).
     81    These laters are on chip communications between processors and coprocessors,
     82    and external communications between the FPGA and the host PC.
     83\end{description}
     84The COACH design flow will be dedicated to system designers, and will as
     85much as possible hide the hardware characteristics to the end user.
     86%From the end user point of view, the specification of the application will be
     87%independant from both the architectural template and from the selected FPGA
     88%family.
    9289
    9390% le programme de travail
    9491\vspace*{.9ex}\par
     92%The COACH project targets fundamental issues related to design methodologies for
     93%digital systems by providing estimation, exploration and design tools targeting both
     94%performance and power optimization at all the abstraction levels of the flow (system,
     95%architecture, algorithm and logic).
     96To reach this ambitious goal, the project will rely on the experience and the
     97complementariness of partners in the following domains:
     98Operating system and communication middleware (\tima, \upmc),
     99MPSoC architectures (\tima, \ubs, \upmc),
     100ASIP architectures (\irisa),
     101High Level Synthesis (\tima, \ubs, \upmc) and loop tranformations (\lip).
     102\\
     103%The CoACH proposal can be described as an extension of the SoCLib virtual
     104%prototyping platform to the FPGA technologies.
     105The COACH project does not start from scratch.
     106It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
     107(DSX, component library), operating systems (MutekH, DNA/OS).
     108It also leverages on  several existing technologies:
     109on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
     110on the ROMA~\cite{roma} project for ASIP,
     111an the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for loop tranformations,
     112and on the \xilinx and \altera IP core libraries.
     113Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
     114bitstreams.
     115\par
     116The COACH proposal has been prepared during one year by a technical working group
     117involving all the academic partners (one monthly meeting from january 2009 to february
     1182010). The objective of these meetings was to analyse the issues of integrating
     119and enhancing the formers tools and tecnnologies into a unique framework allowing to both
     120virtual prototyping and hardware generation.
     121Because the SocLib platform is the base of this project, it may be described as an
     122extension of the SoCLib platform.
     123\par
     124The main development of the COACH project steps are:
     125\begin{enumerate}
     126   \item Definition of the end user inputs:
     127    The coarse grain parallelism of the application will be described as a communicating
     128    task graph, each task being described in C language.
     129    Similarly the architectural templates with their parameters and the design constraints
     130    will be specified.
     131  \item Definition of an internal format for representing task.
     132  \item Development of the GCC pluggin for generating the internal format of a
     133    C task.
     134  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
     135    the internal format. This will allow to swap from one tool to another one, and to
     136    chain them if necessary.
     137  \item Modication of the DSX tool (Design Space eXplorer) of the SocLib
     138    platform to generate the bitstream for the various FPGA families and architectural
     139    templates.
     140  \item Development of new tools such as ASIP compiler, HPC design environment and
     141    dynamic reconfiguration of FPGA devices.
     142\end{enumerate}
     143\par
     144The two major FPGA companies \altera and \xilinx are participating to this
     145project to support the partners providing the software technologies, and to
     146help to generate efficient bitsream for both FPGA families.
     147The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
     148real use cases to benchmark the COACH design environment.
     149\par
     150Following the general policy of the SoCLib platform, the COACH project will be an open
     151infrastructure, available in the framework of the SoCLib server.
     152The architectural templates, and the COACH software tools will be distributed under the
     153GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
     154IP core library) will be freely available for non commercial use. Commercial licences
     155will be negociated for industrial exploitation.
    95156
    96 The COACH project targets fundamental issues related to design methodologies for
    97 digital systems by providing estimation, exploration and design tools targeting both
    98 performance and power optimization at all the abstraction levels of the flow (system,
    99 architecture, algorithm and logic).
    100 
    101 To reach this ambitious aim, this project will lean on the experience and the complementariness
    102 of partners in the following domains: Operating system and hardware
    103 communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
    104 HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
    105 COACH does not start from scratch but relies
    106 on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
    107 SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
    108 ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
    109 
    110 The project objective is to enhance and seamlessly integrate these tools into
    111 a unique open source framework.
    112 The main steps of this project are:
    113 1) Definition of the user inputs: application description as set of communicating tasks, each
    114 task beeing described in the C++ language; architectural template with its parameters; design constraints.
    115 2) Definition of the internal \xcoach format for representing a task.
    116 3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
    117 4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to
    118 swap from one tool to another one and to chain them.
    119 5) Modification of the Design System eXplorator (DSX) of the SocLib platform to let the user
    120 explore the design space and then to generate the bitstream.
    121 %FIXME : a completer
    122 \par
    123 
    124 The two major FPGA companies Altera and Xilinx expect this by supporting
    125 and participating in this project.
    126 The role of the industrial partners BULL, THALES, XXX is to provide real
    127 benchmarks to guide the design of the framework and to prove that COACH is
    128 usuable and cover a large spectrum of applications.
    129 
    130 The COACH arhitectural templates will be freely distributed for non commercial use.
    131 The software tools of COACH will be developped under the General Public Licence.
    132 

  • anr/task-0.tex

    r47 r49  
    55%
    66\begin{objectif}
    7 The objectives of this task are:
     7This task relies to the monitoring of the COACH project. Its main objectives are:
    88\begin{itemize}
    99\item To ensure the appropriate progress of the project.
    … …  
    1212\item To verify the conformance to agreed budget and time scales.
    1313\item To prepare periodic progress reports in order to control the overall progress of the
    14 project.
    15 \item To organize the project meetings (every 3 months).
    16 \item To set up a shared development and dissemination infrastructure as a
    17 version control system and web site.
    18 \item To ensure the dissemination by providing the COACH releases
    19 (milestones and final release) and their associated installation manuals.
     14      project.
     15\item To organize the project meetings.
     16\item To set up a shared development infrastructure as a version control system and
     17      development WEB site.
    2018\end{itemize}
    2119\end{objectif}
    2220%
    2321\begin{workpackage}{D0}
    24 \item This \ST consists of the writing of the consortium agreement and of
    25 having the partners sign it.
     22  \item This \ST consists of the writing of the consortium agreement and of having the
     23    partners sign it.
    2624    \begin{livrable}
    2725    \item{}{0}{6}{d}{\Supmc}{Consortium agreement} A document describing the
    2826        consortium agreement, signed by all the partners.
    2927    \end{livrable}
    30 \item This \ST consists of the managment of deliverables and of the organisation of
    31     project review.
     28  \item This \ST consists of the global management of deliverables and of the global
     29    organization of the project at all the levels.
    3230    \begin{livrable}
    33     \item{}{0}{12}{d}{\Supmc}{First progress report}
    34     \item{}{12}{24}{d}{\Supmc}{Second progress report}
    35     \item{}{24}{36}{d}{\Supmc}{Final report}
     31      \item{}{0}{12}{d}{\Supmc}{First progress report}
     32      \item{}{12}{24}{d}{\Supmc}{Second progress report}
     33      \item{}{24}{36}{d}{\Supmc}{Final report}
     34      \item{}{0}{36}{}{\Supmc}{Global management}
     35        This deliverable corresponds to the global management of the project at all the
     36        levels: progress monitoring, record keeping, meeting organization, review
     37        organization.
    3638    \end{livrable}
    37 \item This \ST consists firstly in the building and maintenance of the
    38 development and dissemination infrastructure. It is also in charge of
    39 distributing the COACH releases.
     39  \item This \ST consists of the project management at the partner level.
     40    It includes mainly the progress monitoring, the record keeping the participation to the
     41    project meetings and the communication with the project leader and other partner.
    4042    \begin{livrable}
    41     \item{}{0}{6}{}{\Supmc}{infrastructure setup} Building the
    42         dissemination infrastructure (web site, wiki, faq) and the
    43         development infrastructure (version control system configuration).
    44     \item{}{6}{36}{}{\Supmc}{dissemination} Providing the COACH
    45     distribution releases and maintaining the dissemination infrastructure.
     43      \item{}{0}{36}{}{\Supmc}{\upmc management} Project management at the partner level.
     44    \end{livrable}
     45  \item This \ST consists firstly in the building and maintenance of the
     46    development and dissemination infrastructure. It is also in charge of
     47    distributing the COACH releases.
     48    \begin{livrable}
     49      \item{V1}{0}{6}{}{\Supmc}{development infrastructure setup}
     50        This deliverable consists of the setup of development infrastructure
     51        (version control system configuration, wiki).
     52      \item{VF}{7}{36}{}{\Supmc}{development infrastructure}
     53        This deliverable corresponds to the standard management of a development
     54        infrastructure (adding \& suppressing account, retrieving forgotten passwords,
     55        creation and closing development branch, ...)
    4656    \end{livrable}
    4757\end{workpackage}

  • anr/task-2.tex

    r48 r49  
    22\let\UPMC\leader
    33\let\IRISA\enable
    4 \let\TIMA\ensable
     4\let\TIMA\enable
    55\end{taskinfo}
    66%

  • anr/task-6.tex

    r40 r49  
    11\begin{taskinfo}
    22\let\IRISA\leader
    3 \let\UPMC\enable
     3\let\BULL\enable
     4\let\THALES\enable
     5\let\NAVTEL\enable
     6\let\ZIED\enable
    47\end{taskinfo}
    58%
    … …  
    1114%
    1215\begin{workpackage}{D6}
    13 \item This \ST is the reference demonstrator. It is an HPC application and so it covers
    14     in addition to HPC (task-5) both the system genration (task-2), the HAS (task-3) and (task-4).
    15     The reference demonstrator can be a Motion JPEG application,
    16     or an application that draws in 3D (under open GL) a simulation of a
    17     metor cloud attracted by a sun and planets,
    18     or a database management system.
     16  \item This \ST relies to the COACH use by \navtel.
     17    The application is A-COMPLETER-1-A-3-LIGNE .... ....  .... .... ....
     18    ... ...
     19    ... ...
     20    ... ...
    1921    \begin{livrable}
    20     \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator specification} Choice of the demonstrator and its
    21     implementation as a PC C/C++ program.
    22     \item{VF}{6}{12}{x}{\Supmc}{reference demonstrator} The demonstrator
    23     split in two parts, a description as a communicating task graph of the FPGA-SoC part.
     22    \item{V1}{0}{6}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}
     23        Choice of the demonstrator and its implementation as a PC C/C++ program.
     24    \item{VF}{7}{12}{x}{\Snavtel}{\navtel \ganttlf demonstrator specification}
     25        The demonstrator is described as a communicating task graph using the
     26        specification defined in the milestone T0+12.
     27    \item{V1}{13}{15}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     28        This deliverable is a report that describes the experimentation done with the
     29        T0+12 COACH milestone.
     30    \item{V2}{25}{27}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     31        This deliverable is a report that describes the experimentation done with the
     32        T0+24 COACH milestone.
     33    \item{VF}{30}{36}{d}{\Snavtel}{\navtel \ganttlf demonstrator}
     34        This deliverable is a report that describes the experimentation done with the
     35        pre-final COACH release.
    2436    \end{livrable}
    2537\end{workpackage}
    2638
    27 
    28 
    29 

  • anr/task-7.tex

    r47 r49  
    55%
    66\begin{objectif}
    7 This task relies to the diffusion the of results.
    8 
     7This task relies to the diffusion of the project results.
     8The objective is to ensure the COACH dissemination by publishing on a public WEB site all
     9the information that a COACH user requires.
     10The main information features are:
     11\begin{itemize}
     12\item The COACH releases (milestones and final release) and their associated installation manuals.
     13\item The COACH user reference manual.
     14\item The user manual of the various tools.
     15\item A COACH tutorial.
     16\item The conference publication.
     17\item A user wiki.
     18\end{itemize}
    919\end{objectif}
    1020%
    1121\begin{workpackage}{D1}
    12 \item This \ST relies on the management of the web site
     22  \item This \ST relies to the management of the WEB site and to the distribution of
     23    the COACH releases.
    1324    \begin{livrable}
    14     \item{V1}{0}{2}{d}{\Supmc}{COACH wiki} Creation of a wiki.
    15     \item{V1}{0}{6}{d}{\Supmc}{COACH web site} Creation and management of the COACH web site.
     25      \item{V1}{0}{6}{d}{\Supmc}{dissemination WEB site}
     26        This deliverable consists firstly in providing a WEB site (name, HTTP server
     27        setup, wiki) and secondly in defining the site map and finally in writting and
     28        installing the pages.
     29      \item{VF}{6}{36}{}{\Supmc}{dissemination WEB site}
     30        This deliverable corresponds to the standard management of a WEB site (modifying,
     31        adding, suppressing, replacing pages).
     32        Especialy the user reference manuals provided in the other tasks will be published
     33        in this site. The published articles will be also be installed in this site.
     34      \item{}{6}{36}{}{\Supmc}{release handling}
     35        This deliverable deals with the elaboration of the COACH software milestones and
     36        final releases with their installation manuals and to publish then into the WEB
     37        site.
    1638    \end{livrable}
    17 \item This \ST relies on the diffusion of the COACH System Generator throught tutorials.
    18     \begin{livrable}
    19     \item{V1}{0}{24}{d}{\Supmc}{UGH - COACH tutorial}
    20         Tutorial presenting UGH.
    21     \item{V2}{0}{30}{d}{\Supmc}{UGH - COACH tutorial}
    22         Tutorial presenting UGH in the CSG.
    23     \item{}{0}{36}{d}{\Supmc}{UGH - COACH tutorial}
    24         Tutorial presenting the final version of COACH using UGH.
    25     \item{V1}{0}{24}{d}{\Subs}{GAUT - COACH tutorial}
    26         Tutorial presenting GAUT.
    27     \item{V2}{0}{30}{d}{\Subs}{GAUT - COACH tutorial}
    28         Tutorial presenting GAUT in the CSG.
    29     \item{}{0}{36}{d}{\Subs}{GAUT - COACH tutorial}
    30         Tutorial presenting the final version of COACH using GAUT.
    31     \end{livrable}
    32 \item This \ST relies on the diffusion of the COACH System Generator throught publications.
    33     \begin{livrable}
    34     \item{V1}{0}{6}{d+x}{\Subs}{specification of \xcoach format}
    35         \setMacroInAuxFile{specXcoachDocI}
    36         First release of the XML specification of the \xcoach format (DTD)
    37         and its associated documentation allowing to start HLS tools development.
    38     \end{livrable}
    39 \item The role of this \ST is to ... \mustbecompleted{FIXME:   A VOIR}
    40     \begin{livrable}
    41     \item{}{0}{6}{d}{\Subs}{macro-cell definition}
    42         The document define the macro cell and the file format describing them.
     39\item This \ST consists of making a COACH tutorial and to publish it on the public WEB
     40    site. The tutorial example will also be used as reference demonstrator of the
     41    framework.
     42    The application of this tutorial can be a Motion JPEG application, or an application
     43    that draws in 3D (under open GL) a simulation of a meteor cloud attracted by a sun and
     44    planets, or a database management system.
     45  \begin{livrable}
     46    \item{V1}{0}{6}{x}{\Supmc}{tutorial specification}
     47        Choice of the application and its implementation as a C/C++ program.
     48    \item{V2}{6}{12}{d+x}{\Supmc}{tutorial}
     49        The application is split into two communicating parts, the PC part and FPGA-SoC part.
     50        Using the features the T0+12 milestone provides,
     51        the tutorial describes how this efficient partionning was obtained.
     52        The FPGA-SoC part is described as communicating task graph. The tutorial also describes
     53        how a promising task graph can be obtained.
     54    \item{V3}{18}{24}{d}{\Supmc}{tutorial}
     55        This tutorial shows how a task can be migrated to coprocessor using HAS tools and
     56        how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
     57        architectural template available in T0+24 milestone.
     58    \item{VF}{30}{36}{d}{\Supmc}{tutorial}
     59        The final release of the tutorial.
    4360    \end{livrable}
    4461\end{workpackage}
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