Changeset 52 for anr/task-2.tex

Timestamp:

Jan 31, 2010, 10:17:25 PM (14 years ago)

Author:

coach

Message:

IA: modification des macros livrable & sortie des tableaux de ressources.

File:

• anr/task-2.tex (modified) (5 diffs)

anr/task-2.tex

@@ -23 +23 @@
 \end{objectif}
 %
-\begin{workpackage}{D2}
+\begin{workpackage}
 \item This \ST corresponds to the Coach System Generator (CSG) software.
     \begin{livrable}
-    \item{V1}{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
+    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
         The first milestone that will allow demonstrators to start working using the COACH
         hardware architecture template.
-    \item{V2}{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
+    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
         This milestone adds to CSG the support to the XILINX and ALTERA architectural
         templates and to the enhanced communication system.
@@ -35 +35 @@
         and ALTERA architectural template.
         HAS is available.
-    \item{V3}{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
+    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
         This milestone extends CSG (\csgPrototypingOnly) to
         FPGA-SoC generation for the XILINX and ALTERA architectural template.
-    \item{VF}{24}{36}{x}{\Supmc}{CSG} Maintenance work of CSG.
+    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:5}
+        Maintenance work of CSG.
     \end{livrable}
 \item This \ST deals with the components of the architectural template.
@@ -51 +52 @@
     application.
     \begin{livrable}
-    \item{}{0}{12}{h}{\Supmc}{COACH architecture} The VHDL synthesizable descriptions
-        of the SocLib MWMR, TokenRing components.
-    \item{V1}{6}{18}{x}{\Stima}{XILINX architecture}
+    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
+        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
+    \itemV{6}{18}{x}{\Stima}{XILINX architecture}
         \setMacroInAuxFile{csgXilinxSystemC}
         The SystemC simulation module of the MWMR component with a PLB bus interface plus
         the SystemC modules of the components of the XILINX architectural template
         not available in the SocLib component library.
-    \item{VF}{18}{24}{h}{\Stima}{XILINX architecture}
+    \itemL{18}{24}{h}{\Stima}{XILINX architecture}{0:0:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgXilinxSystemC).
-    \item{V1}{6}{18}{x}{\Sirisa}{ALTERA architecture}
+    \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
         \setMacroInAuxFile{csgAlteraSystemC}
         The SystemC simulation module of the MWMR component with an AVALON bus interface plus
         the SystemC modules of the components of the ALTERA architectural template
         not available in the SocLib component library.
-    \item{VF}{18}{24}{h}{\Sirisa}{ALTERA architecture}
+    \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgAlteraSystemC);
-    \item{V1}{6}{12}{d}{\Subs}{UBS architecture}
+    \itemV{6}{12}{d}{\Subs}{UBS architecture}
 \mustbecompleted{FIXME:UBS ARGH!!!!!
     1) Attention si vous touchez au MWMR, ils y a 3 composants MWMR.
@@ -77 +78 @@
        Specification of an optimized MWMR component to handle data interleaving (space and time).
        This evolution aims to solve out of order communication weakness of the classical MWMR. 
-    \item{V2}{12}{24}{x}{\Subs}{UBS architecture}
+    \itemV{12}{24}{x}{\Subs}{UBS architecture}
        Release of the tool that generates the VHDL description of the optimized MWMR component
        and its corresponding SystemC module. 
-    \item{VF}{24}{30}{x}{\Subs}{UBS architecture}
+    \itemL{24}{30}{x}{\Subs}{UBS architecture}{0:0:0}
        Final release of the tool that generates the VHDL description of the optimized MWMR component
        and its corresponding SystemC module (\gautMWMRoptimization).
@@ -90 +91 @@
     the NIOS2 and MICROBLAZE processors.
     \begin{livrable}
-    \item{V1}{6}{8}{x}{\Supmc}{MUTEK OS} The drivers required for the first CSG
-    milestone (delivrable \csgCoachArch).
-    \item{V2}{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the
-    second CSG milestone ({\csgPrototypingOnly}).
-    \item{VF}{18}{33}{x}{\Supmc}{MUTEK OS} Maintenance work.
-    \item{}{6}{18}{x}{\upmc}{Port of MUTEK OS}
+    \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
+        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
+    \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
+        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
+    \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}
+        Maintenance work.
+    \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
         Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
-    \item{V1}{6}{8}{x}{\tima}{DNA OS} The drivers required for the first CSG
-    milestone (delivrable \csgCoachArch).
-    \item{V2}{8}{18}{x}{\Stima}{DNA 0S} The drivers required for the
-    second CSG milestone ({\csgPrototypingOnly}).
-    \item{VF}{18}{33}{x}{\Stima}{DNA OS} Maintenance work.
-    \item{}{6}{18}{x}{\tima}{Port of DNA OS}
+    \itemV{6}{8}{x}{\Stima}{DNA OS}
+        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
+    \itemV{8}{18}{x}{\Stima}{DNA 0S}
+        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
+    \itemL{18}{33}{x}{\Stima}{DNA OS}{0:0:0}
+        Maintenance work.
+    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{0:0:0}
         Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     \end{livrable}