Changeset 56 for anr/section-3.1.tex

Timestamp:

Feb 1, 2010, 6:07:27 PM (14 years ago)

Author:

coach

Message:

Modifications de TIMA, task-5 et section-3.1 principalement

File:

• anr/section-3.1.tex (modified) (2 diffs)

anr/section-3.1.tex

@@ +1 @@
+% vim:set spell:
+% vim:spell spelllang=en:
+
 Our project covers several critical domains in system design in order
 to achieve high performance computing. Starting from a high level description we aim 
@@ -4 +7 @@
 
 \subsubsection{High Performance Computing}
-Accelerating high-performance computing (HPC) applications with field-programmable
-gate arrays (FPGAs) can potentially improve performance. 
+% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language
+High-Performance Computing (HPC) world is composed of three main families of architectures:
+many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
+The two first families are dominating the market by taking benefit 
+of the strength and influence of mass-market leaders (Intel, Nvidia)
+%such as Intel for many-core CPU and Nvidia for GPGPU.
+In this market, FPGA architectures are emerging and very promising.
+By adapting architecture to the software, % (the opposite is done in the others families)
+FPGAs architectures enable better performance
+(typically between x10 and x100 accelerations)
+while using smaller size and less energy (and heat).
 However, using FPGAs presents significant challenges~\cite{hpc06a}.
 First, the operating frequency of an FPGA is low compared to a high-end microprocessor.
 Second, based on Amdahl law,  HPC/FPGA application performance is unusually sensitive 
 to the implementation quality~\cite{hpc06b}.
-Finally, High-performance computing programmers are a highly sophisticated but scarce 
-resource. Such programmers are expected to readily use new technology but lack the time 
-to learn a completely new skill such as logic design~\cite{hpc07a} . 
-\\
+% Thus, the performance strongly relies on the detected parallelism.
+% (pour résumer les 2 derniers points)
+Finally, efficient design methodology are required in order to
+hide FPGA complexity and the underlying implantation subtleties to HPC users,
+so that they don't have to change their habits and can have equivalent design productivity
+than in others families~\cite{hpc07a}. 
+
+%état de l'art FPGA 
 HPC/FPGA hardware is only now emerging and in early commercial stages, 
 but these techniques have not yet caught up. 
+Industrial (Mitrionics~\cite{hpc08}, Gidel~\cite{hpc09}, Convey Computer~\cite{hpc10}) and academic (CHREC)
+researches on HPC-FPGA are mainly conducted in the USA. 
+None of the approaches developed in these researches are fulfilling entirely the
+challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in FPGA accelerator,
+but extension generation is not automated and requires hardware design skills.
+Mitrionics has an elegant solution based on a compute engine specifically
+developed for high-performance execution in FPGAs. Unfortunately, the design flow
+is based on a new programming language (mitrionC) implying designer efforts and poor portability.
+% tool relying on operator libraries (XtremeData),  
+% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ?
+
 Thus, much effort is required to develop design tools that translate high level
 language programs to FPGA configurations.
+Moreover, as already remarked in~\cite{hpc11}, Dynamic Partial Reconfiguration~\cite{hpc12}
+(DPR, which enables changing a part of the FPGA, while the rest is still working)
+appears very interesting for improving HPC performance as well as reducing required area.
 
 \subsubsection{System Synthesis}