Changeset 56 for anr/section-4.1.tex

Timestamp:

Feb 1, 2010, 6:07:27 PM (14 years ago)

Author:

coach

Message:

Modifications de TIMA, task-5 et section-3.1 principalement

File:

• anr/section-4.1.tex (modified) (5 diffs)

anr/section-4.1.tex

@@ -11 +11 @@
 \caption{\label{archi-hpc} software architecture of HPC}
 \end{figure}
+%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ?
 %
 Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
@@ -17 +18 @@
 has to provide.
 \vspace*{.75ex}\par
-For the system genration presented in figure~\ref{archi-csg}, the conductor
+For the system generation presented in figure~\ref{archi-csg}, the conductor
 is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
 network describing the application to design and the synthesis parameters.
@@ -32 +33 @@
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
 launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the
-FPGA device.
+FPGA device\footnote{Additional partial bitstreams are generated in case of
+ dynamic partial reconfiguration}.
 \\
 %To proove CSG that COACH is open and CSG is really configurable, COACH will
@@ -65 +67 @@
 other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data
 through communication primitives (tag 2) implemented in a library.
-To evaluate if the relevance of the partitioning, the designer can build a
+The relevance of the partitioning is evaluated through a
 simulator. Once the partitioning is validated, the design of the FPGA part
 is done through \verb!CSG! (figure~\ref{archi-csg}).
+
+
 \vspace*{.75ex}\par
 \mustbecompleted{FIXME == MODIFICATION DE LA FIGURE}
@@ -93 +97 @@
 \item\textbf{Communication between PC \& FPGA-SoC:}
     This task pools the features dedicated to HPC. The main are the
-    partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for
-    both PC and FPGA-SoC sides, the hardware communication components.
+    partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for
+    both PC and FPGA-SoC sides, the hardware communication components and
+        support for dynamic partial reconfiguration.
 \item\textbf{Demonstrators:}
     This task groups the demonstrators of the COACH project.