Changeset 57 for anr/task-5.tex

Timestamp:

Feb 2, 2010, 1:06:38 AM (14 years ago)

Author:

coach

Message:

TIMA scientific justification

File:

• anr/task-5.tex (modified) (3 diffs)

anr/task-5.tex

@@ -58 +58 @@
         \setMacroInAuxFile{hpcMutekDriver}
         The FPGA-SoC part of the communication API, a driver.
-    \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:0:0}
+    \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
         Port of the {\hpcMutekDriver} driver on the DNA OS.
     \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
@@ -66 +66 @@
     architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{0:0:0}
+    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
         \setMacroInAuxFile{hpcPlbBridge}
         The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
@@ -77 +77 @@
 
     \begin{livrable}
-    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}
+    \itemL{18}{36}{x}{\Stima}{CSG support for \ganttlf dynamic reconfiguration}{0:8:12}
         Extension of the \xilinx architectural template ({\csgAllArch})
 in order to integrate dynamic partial reconfiguration regions.
 Modification of CSG software to support the extended \xilinx template.
-    \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0}
+    \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:2:3}
         \setMacroInAuxFile{hpcDynconfDriver}
         The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA.
     \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
         Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
-    \itemL{18}{36}{x}{\Stima}{HPC support for \ganttlf dynamic reconfiguration}{0:0:2}
+    \itemL{24}{36}{x}{\Stima}{HPC profiler for \ganttlf dynamic reconfiguration}{0:0:6}
 Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features
 (reconfiguration time of regions, variable number of coprocessors)