Changeset 87 for anr/section-1.tex

Timestamp:

Feb 3, 2010, 8:04:31 PM (15 years ago)

Author:

coach

Message:

Modifs Christophe

File:

• anr/section-1.tex (modified) (2 diffs)

anr/section-1.tex

@@ -99 +99 @@
 MPSoC architectures (\tima, \ubs, \upmc),
 ASIP architectures (\irisa),
-High Level Synthesis (\tima, \ubs, \upmc) and loop tranformations (\lip).
+High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).
 \\
 %The CoACH proposal can be described as an extension of the SoCLib virtual
@@ -109 +109 @@
 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
 on the ROMA~\cite{roma} project for ASIP,
-an the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for loop tranformations,
+on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
 and on the \xilinx and \altera IP core libraries.
 Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration